The Community for Technology Leaders
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2004)
Portland,Oregon
Dec. 4, 2004 to Dec. 8, 2004
ISSN: 1072-4451
ISBN: 0-7695-2126-6
TABLE OF CONTENTS

list-reviewer (PDF)

pp. xii,xiii

Committees (PDF)

pp. x-xi
Keynote 1
Session 1: Instruction Collapsing

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication (Abstract)

D. Scott Wills , Georgia Institute of Technology
Peter G. Sassone , Georgia Institute of Technology
pp. 7-17

Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth (Abstract)

Anne Bracy , University of Pennsylvania
Prashant Prahlad , University of Pennsylvania
Amir Roth , University of Pennsylvania
pp. 18-29

Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization (Abstract)

Hyunchul Park , University of Michigan - Ann Arbor
Kriszti? Flautner , ARM Ltd., UK
Nathan Clark , University of Michigan - Ann Arbor
Scott Mahlke , University of Michigan - Ann Arbor
Manjunath Kudlur , University of Michigan - Ann Arbor
pp. 30-40
Session 2: Performance Evaluation

MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms (Abstract)

Daniel Gracia P?rez , LRI, Paris Sud/11 University, France
Olivier Temam , LRI, Paris Sud/11 University, France
Gilles Mouchard , LRI, Paris Sud/11 University, France
pp. 43-54

Automatic Synthesis of High-Speed Processor Simulators (Abstract)

Martin Burtscher , Cornell University
Ilya Ganusov , Cornell University
pp. 55-66

Thermal Modeling, Characterization and Management of On-Chip Networks (Abstract)

Amit Kumar , Princeton University, NJ
Li-Shiuan Peh , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
Li Shang , Princeton University, NJ
pp. 67-78
Session 3: Trace Analysis

Pinpointing Representative Portions of Large Intel? Itanium? Programs with Dynamic Instrumentation (Abstract)

Harish Patil , Intel Corporation
Mark Charney , Intel Corporation
Andrew Sun , Intel Corporation
Anand Karunanidhi , Intel Corporation
Rajiv Kapoor , Intel Corporation
Robert Cohn , Intel Corporation
pp. 81-92

The Fuzzy Correlation between Code and Performance Predictability (Abstract)

Bob Davies , Systems Technology Labs (STL)
Richard Hankins , Microarchitecture Research Lab (MRL)
Marzia Polito , Systems Technology Labs (STL)
Ryan Rakvic , Microarchitecture Research Lab (MRL)
Murali Annavaram , Microarchitecture Research Lab (MRL)
Jean-Yves Bouguet , Systems Technology Labs (STL)
pp. 93-104

Whole Execution Traces (Abstract)

Xiangyu Zhang , The University of Arizona, Tucson
Rajiv Gupta , The University of Arizona, Tucson
pp. 105-116
Session 4: Control Flow

Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery (Abstract)

David N. Armstrong , The University of Texas at Austin
Onur Mutlu , The University of Texas at Austin
Yale N. Patt , The University of Texas at Austin
Hyesoon Kim , The University of Texas at Austin
pp. 119-128

Control Flow Optimization Via Dynamic Reconvergence Prediction (Abstract)

Dean M. Tullsen , University of California, San Diego
Jamison D. Collins , University of California, San Diego
Hong Wang , Intel Corporation, Santa Clara, CA
pp. 129-140
Keynote 2
Session 5: Adaptive Microarchitectures

A Case for Clumsy Packet Processors (Abstract)

Arindam Mallik , Northwestern University
Gokhan Memik , Northwestern University
pp. 147-156

Dynamically Trading Frequency for Complexity in a GALS Microprocessor (Abstract)

Grigorios Magklis , University of Rochester
Greg Semeraro , University of Rochester
David H. Albonesi , University of Rochester
Michael L. Scott , University of Rochester
Steven Dropsho , University of Rochester
pp. 157-168
Session 6: Multithreaded/Multicore Processors

Dynamically Controlled Resource Allocation in SMT Processors (Abstract)

Francisco J. Cazorla , Universitat Polit?cnica de Catalunya, Spain
Mateo Valero , Universitat Polit?cnica de Catalunya, Spain
Alex Ramirez , Universitat Polit?cnica de Catalunya, Spain
Enrique Fern?ndez , Universidad de Las Palmas de Gran Canaria, Spain
pp. 171-182

Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy (Abstract)

Brad Calder , University of California at San Diego
Dean M. Tullsen , University of California at San Diego
Eric Tune , University of California at San Diego
Rakesh Kumar , University of California at San Diego
pp. 183-194

Conjoined-Core Chip Multiprocessing (Abstract)

Rakesh Kumar , University of California, San Diego
Norman P. Jouppi , HP Labs, Palo Alto, CA
Dean M. Tullsen , University of California, San Diego
pp. 195-206
Session 7: Security

Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow (Abstract)

Nathan Tuck , University of California, San Diego
George Varghese , University of California, San Diego
Brad Calder , University of California, San Diego
pp. 209-220

Minos: Control Data Attack Prevention Orthogonal to Memory Model (Abstract)

Frederic T. Chong , University of California at Davis
Jedidiah R. Crandall , University of California at Davis
pp. 221-232

A Hardware-Software Platform for Intrusion Prevention (Abstract)

Darko Kirovski , Microsoft Research
Milenko Drinic , Microsoft Research
pp. 233-242

RIFLE: An Architectural Framework for User-Centric Information-Flow Security (Abstract)

Jonathan Chang , Princeton University
Ram Rangan , Princeton University
George A. Reis , Princeton University
Guilherme Ottoni , Princeton University
Jason A. Blome , Princeton University
Neil Vachharajani , Princeton University
David I. August , Princeton University
Manish Vachharajani , Princeton University
Matthew J. Bridges , Princeton University
pp. 243-254
Session 8: Reliability

Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures (Abstract)

Babak Falsafi , Carnegie Mellon University, Pittsburgh, PA
Jangwoo Kim , Carnegie Mellon University, Pittsburgh, PA
James C. Hoe , Carnegie Mellon University, Pittsburgh, PA
Jared C. Smolens , Carnegie Mellon University, Pittsburgh, PA
pp. 257-268

AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants (Abstract)

Pin Zhou , University of Illinois at Urbana-Champaign
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
Shan Lu , University of Illinois at Urbana-Champaign
Feng Qin , University of Illinois at Urbana-Champaign
Long Fei , Purdue University
Wei Liu , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
Samuel Midkiff , Purdue University
pp. 269-280
Session 9: Code Generation and Optimization

Optimal Superblock Scheduling Using Enumeration (Abstract)

Kent Wilken , University of California, Davis
Ghassan Shobaki , University of California, Davis
pp. 283-293

Compiler Optimizations for Transaction Processing Workloads on Itanium? Linux Systems (Abstract)

Knud Kirkegaard , Intel? Compiler Lab, Santa Clara, California
Daniel Lavery , Intel? Compiler Lab, Santa Clara, California
Yong-fong Lee , Intel? Compiler Lab, Santa Clara, California
Gerolf Hoflehner , Intel? Compiler Lab, Santa Clara, California
Rod Skinner , Intel? Compiler Lab, Santa Clara, California
Wei Li , Intel? Compiler Lab, Santa Clara, California
pp. 294-303

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure (Abstract)

Kanad Ghose , State University of New York, Binghamton, NY
Dmitry Ponomarev , State University of New York, Binghamton, NY
Deniz Balkan , State University of New York, Binghamton, NY
Oguz Ergin , Intel Labs, UPC, Barcelona, Spain
pp. 304-315
Session 10: Caches and Memory

Managing Wire Delay in Large Chip-Multiprocessor Caches (Abstract)

David A. Wood , University of Wisconsin-Madison
Bradford M. Beckmann , University of Wisconsin-Madison
pp. 319-330

Cache Refill/Access Decoupling for Vector Machines (Abstract)

Ronny Krashinsky , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Christopher Batten , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanovic , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Steve Gerding , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
pp. 331-342

Adaptive History-Based Memory Schedulers (Abstract)

Ibrahim Hur , The University of Texas at Austin; IBM Corporation, Austin, TX
Calvin Lin , The University of Texas at Austin
pp. 343-354

Memory Controller Optimizations for Web Servers (Abstract)

Scott Rixner , Rice University, Houston, TX
pp. 355-366

Author Index (PDF)

pp. 367
101 ms
(Ver 3.1 (10032016))