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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2003)
San Diego, California
Dec. 3, 2003 to Dec. 5, 2003
ISBN: 0-7695-2043-X
TABLE OF CONTENTS

In memory of Bob Rau (PDF)

M. Schlansker , Hewlett-Packard Laboratories
pp. 165

Committees (PDF)

pp. xi

Reviewers (PDF)

pp. xiii
Keynote 1

null (PDF)

pp. null

Microarchitecture on the MOSFET Diet (PDF)

Kerry Bernstein , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 3
Session 1: Voltage Scaling and Transient Faults

null (PDF)

pp. null

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation (Abstract)

Toan Pham , The University of Michigan, Ann Arbor
Conrad Ziesler , The University of Michigan, Ann Arbor
Trevor Mudge , The University of Michigan, Ann Arbor
Shidhartha Das , The University of Michigan, Ann Arbor
Dan Ernst , The University of Michigan, Ann Arbor
Rajeev Rao , The University of Michigan, Ann Arbor
Sanjay Pant , The University of Michigan, Ann Arbor
Krisztian Flautner , ARM Ltd, Cambridge, UK
Todd Austin , The University of Michigan, Ann Arbor
David Blaauw , The University of Michigan, Ann Arbor
Nam Sung Kim , The University of Michigan, Ann Arbor
pp. 7

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power (Abstract)

Kaushik Roy , Purdue University
Hai Li , Purdue University
T. N. Vijaykumar , Purdue University
Chen-Yong Cher , Purdue University
pp. 19

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor (Abstract)

Todd Austin , University of Michigan
Shubhendu S. Mukherjee , Intel Corporation
Joel Emer , Intel Corporation
Steven K. Reinhardt , Intel Corporation; University of Michigan
Christopher Weaver , Intel Corporation; University of Michigan
pp. 29
Session 2: Cache Design

null (PDF)

pp. null

TLC: Transmission Line Caches (Abstract)

Bradford M. Beckmann , University of Wisconsin, Madison
David A. Wood , University of Wisconsin, Madison
pp. 43

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches (Abstract)

Se-Hyun Yang , Carnegie Mellon University
Babak Falsafi , Carnegie Mellon University
pp. 67
Session 3: Power and Energy Efficient Architectures

null (PDF)

pp. null

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction (Abstract)

Rakesh Kumar , University of California, San Diego
Keith I. Farkas , HP Labs
Dean M. Tullsen , University of California, San Diego
pp. 81

Power-driven Design of Router Microarchitectures in On-chip Networks (Abstract)

Sharad Malik , Princeton University, NJ
Hangsheng Wang , Princeton University, NJ
Li-Shiuan Peh , Princeton University, NJ
pp. 105

Optimum Power/Performance Pipeline Depth (Abstract)

Thomas R. Puzak , IBM - T. J. Watson Research Center, Yorktown Heights, NY
A. Hartstein , IBM - T. J. Watson Research Center, Yorktown Heights, NY
pp. 117
Session 4: Application Specific Optimization and Analysis

null (PDF)

pp. null

Processor Acceleration Through Automated Instruction Set Customization (Abstract)

Nathan Clark , University of Michigan, Ann Arbor
Scott Mahlke , University of Michigan, Ann Arbor
Hongtao Zhong , University of Michigan, Ann Arbor
pp. 129

The Reconfigurable Streaming Vector Processor (RSVP<sup>TM</sup>) (Abstract)

Ray Essick , Motorola Labs, Motorola, Schaumburg, IL
Phil May , Motorola Labs, Motorola, Schaumburg, IL
Silviu Ciricescu , Motorola Labs, Motorola, Schaumburg, IL
Brian Lucas , Motorola Labs, Motorola, Schaumburg, IL
Michael Schuette , Motorola Labs, Motorola, Schaumburg, IL
Ali Saidi , The Mitre Corporation, Bedford, MA
Kent Moat , Motorola Labs, Motorola, Schaumburg, IL
Jim Norris , Motorola Labs, Motorola, Schaumburg, IL
pp. 141

Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice (Abstract)

Richard Hankins , Intel? Corporation
Hubert Nueckel , Intel? Corporation
Murali Annavaram , Intel? Corporation
Brian Hirano , Oracle? Corporation
Trung Diep , Intel? Corporation
John P. Shen , Intel? Corporation
Harald Eri , Oracle? Corporation
pp. 151
Keynote 2

null (PDF)

pp. null

In Memory of Bob Rau (PDF)

Michael Schlansker , Hewlett-Packard Laboratories
pp. 165
Session 5: Dynamic Optimization Systems

null (PDF)

pp. null

The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System (Abstract)

Howard Chen , University of Minnesota, Twin Cities
Bobbie Othmer , University of Minnesota, Twin Cities
Pen-Chung Yew , University of Minnesota, Twin Cities
Jiwei Lu , University of Minnesota, Twin Cities
Dong-Yuan Chen , Intel Corporation
Wei-Chung Hsu , University of Minnesota, Twin Cities
Rao Fu , University of Minnesota, Twin Cities
pp. 180
Session 6: Dynamic Program Analysis and Optimization

null (PDF)

pp. null

LLVA: A Low-level Virtual Instruction Set Architecture (Abstract)

Michael Brukman , University of Illinois at Urbana-Champaign
Vikram Adve , University of Illinois at Urbana-Champaign
Chris Lattner , University of Illinois at Urbana-Champaign
Anand Shukla , University of Illinois at Urbana-Champaign
Brian Gaeke , University of Illinois at Urbana-Champaign
pp. 205

Comparing Program Phase Detection Techniques (Abstract)

James E. Smith , University of Wisconsin - Madison
Ashutosh S. Dhodapkar , University of Wisconsin - Madison
pp. 217

Using Interaction Costs for Microarchitectural Bottleneck Analysis (Abstract)

Mark D. Hill , University of Wisconsin-Madison
Chris J. Newburn , Intel Corporation
Rastislav Bod? , University of California-Berkeley
Brian A. Fields , University of California-Berkeley
pp. 228
Session 7: Branch, Value and Scheduling Optimizations

null (PDF)

pp. null

Fast Path-Based Neural Branch Prediction (Abstract)

Daniel A. Jim?nez , Rutgers University, Piscataway, NJ
pp. 243

Hardware Support for Control Transfers in Code Caches (Abstract)

Ho-Seop Kim , University of Wisconsin - Madison
James E. Smith , University of Wisconsin - Madison
pp. 253

Exploiting Value Locality in Physical Register Files (Abstract)

Saisanthosh Balakrishnan , University of Wisconsin-Madison
Gurindar S. Sohi , University of Wisconsin-Madison
pp. 265

Macro-op Scheduling: Relaxing Scheduling Loop Constraints (Abstract)

Mikko H. Lipasti , University of Wisconsin, Madison
Ilhyun Kim , University of Wisconsin, Madison
pp. 277
Session 8: Dataflow, Data Parallel, and Clustered Architectures

null (PDF)

pp. null

WaveScalar (Abstract)

Mark Oskin , University of Washington
Ken Michelson , University of Washington
Andrew Schwerin , University of Washington
Steven Swanson , University of Washington
pp. 291

Universal Mechanisms for Data-Parallel Architectures (Abstract)

Karthikeyan Sankaralingam , The University of Texas at Austin
William R. Mark , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
pp. 303

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors (Abstract)

Jes? S?nchez , Intel Labs - Universitat Polit?cnica de Catalunya
Enric Gibert , Universitat Polit?cnica de Catalunya
Antonio Gonz?lez , Universitat Polit?cnica de Catalunya; Intel Labs - Universitat Polit?cnica de Catalunya
pp. 315

Instruction Replication for Clustered Microarchitectures (Abstract)

Antonio Gonz?lez , UPC, Barcelona, Spain; Intel Barcelona Research Center, Intel Labs, UPC, Barcelona, Spain
Alex Alet? , UPC, Barcelona, Spain
Josep M. Codina , UPC, Barcelona, Spain
David Kaeli , Northeastern University, Boston, MA, USA
pp. 326
Session 9: Secure and Network Processors

null (PDF)

pp. null

Efficient Memory Integrity Verification and Encryption for Secure Processors (Abstract)

Blaise Gassend , MIT Computer Science and Artificial Intelligence Laboratory
Dwaine Clarke , MIT Computer Science and Artificial Intelligence Laboratory
Marten van Dijk , MIT Computer Science and Artificial Intelligence Laboratory
G. Edward Suh , MIT Computer Science and Artificial Intelligence Laboratory
Srinivas Devadas , MIT Computer Science and Artificial Intelligence Laboratory
pp. 339

Fast Secure Processor for Inhibiting Software Piracy and Tampering (Abstract)

Lan Gao , University of California, Riverside
Youtao Zhang , University of Texas at Dallas
Jun Yang , University of California, Riverside
pp. 351

IPStash: a Power-Efficient Memory Architecture for IP-lookup (Abstract)

Georgios Keramidas , University of Patras, Greece
Stefanos Kaxiras , University of Patras, Greece
pp. 361

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers (Abstract)

Lloren? Cerd? , Polytechnic University of Catalonia
Mateo Valero , Polytechnic University of Catalonia
Jorge Garc? , Polytechnic University of Catalonia
Jes? Corbal , Polytechnic University of Catalonia
pp. 373
Session 10: Scaling Design

null (PDF)

pp. null

Beating in-order stalls with "flea-flicker" two-pass pipelining (Abstract)

Nacho Navarro , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
John W. Sias , University of Illinois at Urbana-Champaign
Ronald D. Barnes , University of Illinois at Urbana-Champaign
Wen-mei W. Hwu , University of Illinois at Urbana-Champaign
Erik M. Nystrom , University of Illinois at Urbana-Champaign
pp. 387

Scalable Hardware Memory Disambiguation for High ILP Processors (Abstract)

Rajagopalan Desikan , The University of Texas at Austin
Simha Sethumadhavan , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Charles R. Moore , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
pp. 399

Reducing Design Complexity of the Load/Store Queue (Abstract)

Chong Liang Ooi , Purdue University
Il Park , Purdue University
T. N. Vijaykumar , Purdue University
pp. 411

Author Index (PDF)

pp. 435
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