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Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. (2003)
San Diego, California
Dec. 3, 2003 to Dec. 5, 2003
ISBN: 0-7695-2043-X
pp: 339
G. Edward Suh , MIT Computer Science and Artificial Intelligence Laboratory
Dwaine Clarke , MIT Computer Science and Artificial Intelligence Laboratory
Blaise Gassend , MIT Computer Science and Artificial Intelligence Laboratory
Marten van Dijk , MIT Computer Science and Artificial Intelligence Laboratory
Srinivas Devadas , MIT Computer Science and Artificial Intelligence Laboratory
ABSTRACT
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks. This paper proposes new hardware mechanisms for memory integrity verification and encryption, which are two key primitives required in single-chip secure processors. The integrity verification mechanism offers significant performance advantages over existing ones when the checks are infrequent as in grid computing applications. The encryption mechanism improves the performance in all cases.
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CITATION

B. Gassend, D. Clarke, M. v. Dijk, G. E. Suh and S. Devadas, "Efficient Memory Integrity Verification and Encryption for Secure Processors," Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.(MICRO), San Diego, California, 2003, pp. 339.
doi:10.1109/MICRO.2003.1253207
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