The Community for Technology Leaders
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2003)
San Diego, California
Dec. 3, 2003 to Dec. 5, 2003
ISBN: 0-7695-2043-X
pp: 228
Mark D. Hill , University of Wisconsin-Madison
Chris J. Newburn , Intel Corporation
Rastislav Bod? , University of California-Berkeley
Brian A. Fields , University of California-Berkeley
ABSTRACT
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a cost to an event (e.g., to one of two overlapping cache misses) and (b) assign blame for each cycle (e.g., for a cycle where many, overlapping resources are active). This paper introduces a new model for understanding event costs to facilitate processor design and optimization.<div></div> First, we observe that everything in a machine (instructions, hardware structures, events) can interact in only one of two ways (in parallel or serially). We quantify these interactions by defining interaction cost, which can be zero (independent, no interaction), positive (parallel), or negative (serial).<div></div> Second, we illustrate the value of using interaction costs in processor design and optimization.<div></div> Finally, we propose performance-monitoring hardware for measuring interaction costs that is suitable for modern processors.
INDEX TERMS
null
CITATION
Mark D. Hill, Chris J. Newburn, Rastislav Bod?, Brian A. Fields, "Using Interaction Costs for Microarchitectural Bottleneck Analysis", 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, vol. 00, no. , pp. 228, 2003, doi:10.1109/MICRO.2003.1253198
108 ms
(Ver )