Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. (2003)
San Diego, California
Dec. 3, 2003 to Dec. 5, 2003
Rakesh Kumar , University of California, San Diego
Keith I. Farkas , HP Labs
Norman P. Jouppi , HP Labs
Parthasarathy Ranganathan , HP Labs
Dean M. Tullsen , University of California, San Diego
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cores representing different points in the power/performance design space; during an application?s execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements.<div></div> Our evaluation of this architecture shows significant energy benefits. For an objective function that optimizes for energy efficiency with a tight performance threshold, for 14 SPEC benchmarks, our results indicate a 39% average energy reduction while only sacrificing 3% in performance. An objective function that optimizes for energy-delay with looser performance bounds achieves, on average, nearly a factor of three improvement in energy-delay product while sacrificing only 22% in performance. Energy savings are substantially more than chip-wide voltage/frequency scaling.
N. P. Jouppi, R. Kumar, K. I. Farkas, P. Ranganathan and D. M. Tullsen, "Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction," Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.(MICRO), San Diego, California, 2003, pp. 81.