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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2002)
Istanbul, Turkey
Nov. 18, 2002 to Nov. 22, 2002
ISSN: 1072-4451
ISBN: 0-7695-1959-1
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Session 1: Superscalar Design

Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors (Abstract)

Michael C. Huang , University of Rochester
José F. Martínez , Cornell University
Milos Prvulovic , University of Illinois at Urbana-Champaign
Jose Renau , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 3

Characterizing and Predicting Value Degree of Use (Abstract)

Gurindar S. Sohi , University of Wisconsin-Madison
J. Adam Butts , University of Wisconsin-Madison
pp. 15

Hierarchical Scheduling Windows (Abstract)

Bryan Black , Intel Labs
Jeff Rupley II , Intel Labs
Edward Brekelbaum , Intel Labs
Chris Wilkerson , Intel Labs
pp. 27

Three Extensions To Register Integration (Abstract)

Anne Bracy , University of Pennsylvania
Amir Roth , University of Pennsylvania
Vlad Petric , University of Pennsylvania
pp. 37
Session 2: Multithreading I

Instruction Fetch Deferral using Static Slack (Abstract)

Sanjay J. Patel , University of Illinois at Urbana-Champaign
Gregory A. Muthler , University of Illinois at Urbana-Champaign
Steven S. Lumetta , University of Illinois at Urbana-Champaign
David Crowe , University of Illinois at Urbana-Champaign
pp. 51

Pointer Cache Assisted Prefetching (Abstract)

Suleyman Sair , University of California, San Diego
Brad Calder , University of California, San Diego
Dean M. Tullsen , University of California, San Diego
Jamison Collins , University of California, San Diego
pp. 62

Microarchitectural Support for Precomputation Microthreads (Abstract)

Robert S. Chappell , The University of Michigan
Yale N. Patt , The University of Texas at Austin
Adi Yoaz , Intel Corporation
Francis Tseng , The University of Texas at Austin
pp. 74

Master/Slave Speculative Parallelization (Abstract)

Gurindar Sohi , University of Wisconsin at Madison
Craig Zilles , University of Illinois at Urbana-Champaign
pp. 85
Session 3: Compiler Scheduling

Reduced Code Size Modulo Scheduling in the Absence of Hardware Support (Abstract)

Josep Llosa , Universitat Polit?cnica de Catalunya
Stefan M. Freudenberger , Hewlett-Packard Laboratories
pp. 99

Convergent Scheduling (Abstract)

Diego Puppin , Massachusetts Institute of Technology
Shane Swenson , Massachusetts Institute of Technology
Saman Amarasinghe , Massachusetts Institute of Technology
Walter Lee , Massachusetts Institute of Technology
pp. 111

Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor (Abstract)

Antonio González , Intel Labs - Universitat Polit?cnica de Catalunya
Jesús Sánchez , Intel Labs - Universitat Polit?cnica de Catalunya
Enric Gibert , Universitat Polit?cnica de Catalunya
pp. 123

Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors (Abstract)

Li-Ling Chen , Intel Corporation
Youfeng Wu , Intel Corporation
Ryan Rakvic , Intel Corporation
George Chrysos , Intel Corporation
Jesse Fang , Intel Corporation
Chyi-Chang Miao , Intel Corporation
pp. 134
Session 4: Register File and Memory System Design

Three-Dimensional Memory Vectorization for High Bandwidth Media Memory Systems (Abstract)

Mateo Valero , Universitat Polit?cnica de Catalunya
Roger Espasa , Universitat Polit?cnica de Catalunya
Jesus Corbal , Universitat Polit?cnica de Catalunya
pp. 149

Dynamic Addressing Memory Arrays with Physical Locality (Abstract)

Shih-Lien Lu , Intel Corporation
Steven Hsu , Intel Corporation
Shih-Chang Lai , Oregon State University
Konrad Lai , Intel Corporation
Ram Krishnamurthy , Intel Corporation
pp. 161

Reducing Register Ports for Higher Speed and Lower Energy (Abstract)

T.N. Vijaykumar , Purdue University
Michael D. Powell , Purdue University
Il Park , Purdue University
pp. 171
Session 5: Energy Efficient Memory Systems

Generating Physical Addresses Directly for Saving Instruction TLB Energy (Abstract)

G. Chen , Pennsylvania State University
M. Kandemir , Pennsylvania State University
A. Sivasubramaniam , Pennsylvania State University
I. Kadayif , Pennsylvania State University
G. Kandiraju , Pennsylvania State University
pp. 185

Energy Efficient Frequent Value Data Cache Design (Abstract)

Rajiv Gupta , University of Arizona
Jun Yang , University of California, Riverside
pp. 197

Compiler-Directed Instruction Cache Leakage Optimization (Abstract)

M.J. Irwin , Pennsylvania State University
V. Degalahal , Pennsylvania State University
J.S. Hu , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. Kandemir , Pennsylvania State University
W. Zhang , Pennsylvania State University
pp. 208

Leakage Power Reduction using Dynamic Voltage Scaling and Cahe Sub-bank Prediction (Abstract)

David Blaauw , University of Michigan
Nam Sung Kim , University of Michigan
Trevor Mudge , University of Michigan
pp. 219
Session 6: Compilation and Run-time Systems

Vacuum Packing: Extracting Hardware-Detected Program Phases for Post-Link Optimization (Abstract)

Erik M. Nystrom , University of Illinois at Urbana-Champaign
Wen-mei W. Hwu , University of Illinois at Urbana-Champaign
Ronald D. Barnes , University of Illinois at Urbana-Champaign
Matthew C. Merten , University of Illinois at Urbana-Champaign
pp. 233

A Faster Optimal Register Allocator (Abstract)

Kent Wilken , University of California, Davis
Changqing Fu , University of California, Davis
pp. 245

DELI: A New Run-Time Control Point (Abstract)

Giuseppe Desoli , Hewlett-Packard Laboratories
Nikolay Mateev , Hewlett-Packard Laboratories
Paolo Faraboschi , Hewlett-Packard Laboratories
Joseph A. Fisher , Hewlett-Packard Laboratories
Evelyn Duesterwald , Hewlett-Packard Laboratories
pp. 257
Session 7: Simulation and Architecture Evaluation

Microarchitectural Exploration with Liberty (Abstract)

David A. Penry , Princeton University
Neil Vachharajani , Princeton University
David I. August , Princeton University
Jason A. Blome , Princeton University
Manish Vachharajani , Princeton University
pp. 271

Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks (Abstract)

David Patterson , University of California at Berkeley
Christoforos Kozyrakis , Stanford University
pp. 283

Orion: A Power-Performance Simulator for Interconnection Networks (Abstract)

Hang-Sheng Wang , Princeton University
Li-Shiuan Peh , Princeton University
Xinping Zhu , Princeton University
Sharad Malik , Princeton University
pp. 294

Using Modern Graphics Architectures for General-Purpose Computing: A Framework and Analysis (Abstract)

Mark Oskin , University of Washington
Sahngyun Hahn , University of Washington
Chris J. Thompson , University of Washington
pp. 306
Session 8: Energy Aware Design

Managing Static Leakage Energy in Microprocessor Functional Units (Abstract)

Eby G. Friedman , University of Rochester
Volkan Kursun , University of Rochester
Sandhya Dwarkadas , University of Rochester
Steven Dropsho , University of Rochester
David H. Albonesi , University of Rochester
pp. 321

Optimizing Pipelines for Power and Performance (Abstract)

Michael Gschwind , IBM T.J. Watson Research Center
Pradip Bose , IBM T.J. Watson Research Center
David Brooks , IBM T.J. Watson Research Center
Philip N. Strenski , IBM T.J. Watson Research Center
Victor Zyuban , IBM T.J. Watson Research Center
Viji Srinivasan , IBM T.J. Watson Research Center
Philip G. Emma , IBM T.J. Watson Research Center
pp. 333

Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses (Abstract)

M. Kandemir , Pennsylvania State University
A. Choudhary , Northwestern University
J. Pisharath , Northwestern University
K. Basu , Northwestern University
pp. 345

Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture (Abstract)

Grigorios Magklis , University of Rochester
Greg Semeraro , University of Rochester
Steven G. Dropsho , University of Rochester
Michael L. Scott , University of Rochester
Sandhya Dwarkadas , University of Rochester
David H. Albonesi , University of Rochester
pp. 356
Session 9: Superscalar Microarchitecture

Fetching instruction streams (Abstract)

Mateo Valero , Universitat Politecnica de Catalunya
Josep L. Larriba-Pey , Universitat Politecnica de Catalunya
Oliverio J. Santana , Universitat Politecnica de Catalunya
Alex Ramirez , Universitat Politecnica de Catalunya
pp. 371
Session 10: Multithreading II

Microarchitectural Denial of Service: Insuring Microarchitectural Fairness (Abstract)

Soraya Ghiasi , University of Colorado
Dirk Grunwald , University of Colorado
pp. 409

Compiling for Instruction Cache Performance on a Multithreaded Architecture (Abstract)

Rakesh Kumar , University of California, San Diego
Dean M. Tullsen , University of California, San Diego
pp. 419

A Quantitative Framework for Automated Pre-Execution Thread Selection (Abstract)

Amir Roth , University of Pennsylvania
Gurindar S. Sohi , University of Wisconsin-Madison
pp. 430

Author Index (PDF)

pp. 443
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