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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2000)
Monterey, California
Dec. 10, 2000 to Dec. 13, 2000
ISBN: 0-7695-0924-x
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. ix

Committees (PDF)

pp. xi

Revievers (PDF)

pp. xiii
Keynote Speakers
Memory Hierarchy I

Eager Writeback - a Technique for Improving Bandwidth Utilization (Abstract)

Matthew K. Farrend , University of California
Gary S. Tyson , University of Michigan
Hsien-Hsin S. Lee X , University of Michigan
pp. 11

Silent Stores for Free (Abstract)

Mikko H. Lipasti , University of Wisconsin
Kevin M. Lepak , University of Wisconsin
pp. 22

A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality (Abstract)

Zhao Zhang , College of William and Mary
Xiaodong Zhang , College of William and Mary
Zhichun Zhu , College of William and Mary
pp. 32

Predictor-Directed Stream Buffers (Abstract)

Suleyman Sair , University of California, San Diego
Timothy Sherwood , University of California, San Diego
Brad Calder , University of California, San Diego
pp. 42
Superscalar Architecture I

On Pipelining Dynamic Instruction Scheduling Logic (Abstract)

Yale N. Patt , The University of Texas at Austin
Jared Stark , Intel Corporation
Mary D. Brown , The University of Texas at Austin
pp. 57

The Impact of Delay on the Design of Branch Predictors (Abstract)

Calvin Lin , The University of Texas at Austin
Daniel A. JimCnez , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
pp. 67

Improving BTB Performance in the Presence of DLLs (Abstract)

Gary S. Tyso , The University of Michigan
Stevan Vlaovic , The University of Michigan
Edward S. Davidson , The University of Michigan
pp. 77

Efficient Checker Processor Design (Abstract)

Chris Weaver , University of Michigan
Saugata Chatterjee , University of Michigan
Todd Austin , University of Michigan
pp. 87
Compilation

An Integrated Approach to Accelerate Data and Predicate Computations in Hyperblocks (Abstract)

Alexandre Eichenberger , North Carolina State University, Raleigh, NC
Waleed Meleis , Northeastern University, Boston, MA
Suman Maradani , Northeastern University, Boston, MA
pp. 101

Accurate and Efficient Predicate Analysis with Binary Decision Diagrams (Abstract)

Wen-mei W. Hwu , University of Illinois
David I. August , Department of Computer Science Princeton University
pp. 112

Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture (Abstract)

Antonio Gonzalez , Universitat Politbcnica de Catalunya
Jestis Sanchez , Universitat Politbcnica de Catalunya
pp. 124
Accelerator Architecture

Two-level Hierarchical Register File Organization for VLIW Processors (Abstract)

Eduard Ayguade , Universitat Polithnica de Catalunya
Josep Llosa , Universitat Polithnica de Catalunya
Javier Zalamea , Universitat Polithnica de Catalunya
Mateo Valero , Universitat Polithnica de Catalunya
pp. 137

PipeRench Implementation of the Instruction Path Coprocessor (Abstract)

John Pau , Carnegie Mellon University
Herman Schmit , Carnegie Mellon University
Pazhani Pillai , Carnegie Mellon University
Yuan Chou , Carnegie Mellon University
pp. 147

Efficient Conditional Operations for Data-parallel Architectures (Abstract)

William J. Dally , Stanford University
Brucek Khailany , Stanford University
Scott Rixner , Stanford University
Ujval J. Kapasi , Stanford University
John D. Owens , Stanford University
Peter R. Mattson , Stanford University
pp. 159
Low-Power Design

A Static Power Model for Architects (Abstract)

Gurindar S. Sohi , University of Wisconsin-Madison
J. Adam Butts , University of Wisconsin-Madison
pp. 191

A framework for Dynamic Energy Efficiency and Josep Temperature Management (Abstract)

Seung-Moon Yoo , University Of Illinois at Urbana-Champaign
Micheal Huang , University Of Illinois at Urbana-Champaign
Josep Torrellas , University Of Illinois at Urbana-Champaign
Jose Renau , University Of Illinois at Urbana-Champaign
pp. 202

Dynamic Zero Compression for Cache Energy Reduction (Abstract)

Michael Zhang , MIT Laboratory for Computer, Science
Krste Asanovie , MIT Laboratory for Computer, Science
pp. 214
Memory Hierarchy II

Register Integration: A Simple and Efficient Implementation of Squash Reuse (PDF)

Gurindar S. Sohi , Computer Sciences Department, University of Wisconsin
Amir Roth , Computer Sciences Department, University of Wisconsin
pp. 223

Memory Hierarchy Reconfigurtion for Energy and Performance in General-Purpose Processor Architectures (Abstract)

David Albonesi , University of Rochester
Rajeev Balasubramonian , University of Rochester
Sandhya Dwarkadas , University of Rochester
Alper Buyuktosunoglu , University of Rochester
pp. 245

Frequent Value Compression in Data Caches (Abstract)

Youtao Zhang , The University of Arizona, Tucson, AZ 85721
Rajiv Gupta , The University of Arizona, Tucson, AZ 85721
Jun Yang , The University of Arizona, Tucson, AZ 85721
pp. 258
Dynamic Translation and Multithreading

Increasing the Size of Atomic Instruction Blocks using Control Flow Assertions (Abstract)

Matthew M. Crum , University of Illinois at Urbana-Champaign
Tony Tung , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
Satarupa Bose , University of Illinois at Urbana-Champaign
pp. 303
Superscalar Architecture II

Reducing Wire Delay Penalty through Value Prediction (Abstract)

Joan-Manuel Parcerisa , Dept. d' Arquitectura de Computadors, Universitat Politecnica de Catalunya
Antonio Gonzalez , Dept. d' Arquitectura de Computadors, Universitat Politecnica de Catalunya
pp. 317

Compiler Conrolled Value Prediction using Branch Predictor Based confidence (Abstract)

Eric Larson , University of Michigan
Todd Austin , University of Michigan
pp. 327
Author Index

Author Index (PDF)

pp. 337
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