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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (1999)
Haifa, Israel
Nov. 16, 1999 to Nov. 18, 1999
ISSN: 1072-4451
ISBN: 0-7695-0437-X
TABLE OF CONTENTS

Foreword (PDF)

pp. ix

Committees (PDF)

pp. x

Reviewers (PDF)

pp. xii
Session 1: Welcome and Keynote: Chair: Uri Weiser, Intel
Session 2: Faster FrontEnd: Chair: Gary Tyson, The University of Michigan, Ann Arbor

Control Independence in Trace Processors (Abstract)

Eric Rotenberg , North Carolina State University
Jim Smith , University of Wisconsin at Madison
pp. 4

Fetch Directed Instruction Prefetching (Abstract)

Todd Austin , University of Michigan
Glenn Reinman , University of California at San Diego
Brad Calder , University of California at San Diego
pp. 16

Improving Branch Predictors by Correlating on Data Values (Abstract)

J.E. Smith , University of Wisconsin at Madison
Zak Smith , Hewlett-Packard
Timothy H. Heil , University of Wisconsin at Madison
pp. 28

Instruction Fetch Mechanisms for Multipath Execution Processors (Abstract)

Artur Klauser , University of Colorado at Boulder
Dirk Grunwald , University of Colorado at Boulder
pp. 38
Session 3: 3D and MultiMedia: Chair: Matthew Farrens, University of California, Davis

A Superscalar 3D Graphics Engine (Abstract)

Andrew Wolfe , S3 Incorporated
Derek B. Noonburg , S3 Incorporated
pp. 50

Dynamic 3D Graphics Workload Characterization and the Architectural Implications (Abstract)

Tulika Mitra , State University of New York at Stony Brook
Tzi-cker Chiueh , State University of New York at Stony Brook
pp. 62

Exploiting a New Level of DLP in Multimedia Applications (Abstract)

Mateo Valero , Universitat Polit?cnica de Catalunya
Jesus Corbal , Universitat Polit?cnica de Catalunya
Roger Espasa , Compaq Computer Corporation
pp. 72
Session 4: Efficient Embedded Processors: Chair: Kemal Ebcioglu, IBM

Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors (Abstract)

Thomas M. Conte , North Carolina State University at Raleigh
Sergei Y. Larin , North Carolina State University at Raleigh
pp. 82

Evaluation of a High Performance Code Compression Method (Abstract)

Charles Lefurgy , University of Michigan
Trevor Mudge , University of Michigan
Eva Piccininni , University of Michigan
pp. 93

Low-Cost Branch Folding for Embedded Applications with Small Tight Loops (Abstract)

Jeff , Motorola Incorporated
Lea Hwang Lee , Motorola Incorporated
Bill Moyer , Motorola Incorporated
John Arends , Motorola Incorporated
Scott , Motorola Incorporated
pp. 103
Session 5: Memory Hierarchy: Chair: Doug Burger, University of Texas, Austin

Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems (Abstract)

Santosh G. Abraham , Hewlett-Packard Laboratories
Scott A. Mahlke , Hewlett-Packard Laboratories
pp. 114

Hardware Identification of Cache Conflict Misses (Abstract)

Jamison D. Collins Dean M. Tullsen , University of California at San Diego
pp. 126

Access Region Locality for High-Bandwidth Processor Memory System Design (Abstract)

Pen-Chung Yew , University of Minnesota
Gyungho Lee , Iowa State University
Sangyeun Cho , Samsung Electronics Corporation
pp. 136

Code Transformations to Improve Memory Parallelism (Abstract)

Sarita Adve , University of Illinois
Vijay S. Pai , Rice University
pp. 147
Session 6: Better Scheduling: Chair: Stephan Jourdan, Intel

Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results (Abstract)

Wen-mei W. Hwu , University of Illinois at Urbana
Daniel A. Connors , University of Illinois at Urbana
pp. 158

Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing (Abstract)

Soner Onder , Michigan Technological University
Rajiv Gupta , The University of Arizona
pp. 170

Read-After-Read Memory Dependence Prediction (Abstract)

Gurindar S. Sohi , University of Wisconsin at Madison
Andreas Moshovos , Northwestern University
pp. 177

Delaying Physical Register Allocation through Virtual-Physical Registers (Abstract)

José González , University de Zaragoza
Antonio González , University de Zaragoza
Mateo Valero , University de Zaragoza
Victor Viñals , Universitat Polit?cnica de Catalunya
Teresa Monreal , Universitat Polit?cnica de Catalunya
pp. 186
Session 7: Invited Speaker: Chair: Gabby Silberman, IBM, Canada
Session 8: Novel Microarchitectures and Multithreading: Chair: Brad Calder, University of California, San Diego

Exploiting ILP in Page-Based Intelligent Memory (Abstract)

Diana Keen , University of California at Davis
Frederic T. Chong , University of California at Davis
Mark Oskin , University of California at Davis
Aneet Chopra , University of California at Davis
Justin Hensley , University of California at Davis
Matthew Farrens , University of California at Davis
pp. 208

The Use of Multithreading for Exception Handling (Abstract)

Joel S. Emer , Compaq Computer Corporation
Gurindar S. Sohi , University of Wisconsin at Madison
Craig B. Zilles , University of Wisconsin at Madison
pp. 219

Value Prediction for Speculative Multithreaded Architectures (Abstract)

Pedro Marcuello , Universitat Polit?cnica de Catalunya
Jordi Tubella , Universitat Polit?cnica de Catalunya
Antonio González , Universitat Polit?cnica de Catalunya
pp. 230
Session 9: Low Power Enhancements: Chair: Mateo Valero, Universitat Politecnica de Catalunya, Spain
Session 10: Compilers: Chair: David Bernstein, IBM, Israel

Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs (Abstract)

Chris McKinsey , Motorola Incorporated
Jay Bharadwaj , Intel Corporation
Kishore Menezes , Intel Corporation
pp. 262

Balance Scheduling: Weighting Branch Tradeoffs in Superblocks (Abstract)

Alexandre E. Eichenberger , North Carolina State University
Waleed M. Meleis , Northeastern University
pp. 272

Optimizations and Oracle Parallelism with Dynamic Translation (Abstract)

Kemal Ebcioglu , IBM Thomas J. Watson Research Center
Sumedh Sathaye , IBM Thomas J. Watson Research Center
Michael Gschwind , IBM Thomas J. Watson Research Center
Erik R. Altman , IBM Thomas J. Watson Research Center
pp. 284
Session 11: Summary and Awards

Index of Authors (PDF)

pp. 299
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