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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (1997)
Research Triangle Park, NC
Dec. 1, 1997 to Dec. 3, 1997
ISSN: 1072-4451
ISBN: 0-8186-7977-8
TABLE OF CONTENTS

Foreword (PDF)

pp. viii

Reviewers (PDF)

pp. xi
Session 1: Instruction Fetch: Chair: Brad Calder, University of California, San Diego

The Bi-Mode Branch Predictora (Abstract)

Trevor Mudge , University of Michigan
I-Cheng Chen , University of Michigan
Chih-Chieh Lee , University of Michigan
pp. 4

Path-Based Next Trace Prediction (Abstract)

Eric Rotenberg , University of Wisconsin - Madison
Quinn Jacobson , University of Wisconsin - Madison
James E. Smith , University of Wisconsin - Madison
pp. 14

Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism (Abstract)

Sanjay J. Patel , Advanced Computer Architecture Laboratory University of Michigan
Daniel H. Friendly , Advanced Computer Architecture Laboratory University of Michigan
Yale N. Patt , Advanced Computer Architecture Laboratory University of Michigan
pp. 24
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments

On High-Bandwidth Data Cache Design for Multi-Issue Processors (Abstract)

Gary S. Tyson , The University of Michigan
Todd M. Austin , MicroComputer Research Labs Intel Corporation
Jude A. Rivers , The University of Michigan
Edward S. Davidson , The University of Michigan
pp. 46

Run-time Spatial Locality Detection and Optimization (Abstract)

Matthew C. Merten , Center for Reliable and High-Performance Computing University of Illinois
Wen-mei W. Hwu , Center for Reliable and High-Performance Computing University of Illinois
Teresa L. Johnson , Center for Reliable and High-Performance Computing University of Illinois
pp. 57

The design and performance of a conflict-avoiding cache (Abstract)

J. Gonzalez , Dept. of Comput. Sci., Edinburgh Univ., UK
A. Gonzalez , Dept. of Comput. Sci., Edinburgh Univ., UK
N. Topham , Dept. of Comput. Sci., Edinburgh Univ., UK
pp. 71

Prediction Caches for Superscalar Processors (Abstract)

James E. Bennett , Stanford University
Michael J. Flynn , Stanford University
pp. 81
Session 3: ILP Compiler Techniques I: Chair: Jim Dehnert, Silicon Graphics, Inc.

A framework for balancing control flow and predication (Abstract)

D.I. August , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
S.A. Mahlke , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 92

Evaluation of scheduling techniques on a SPARC-based VLIW testbed (Abstract)

Seongbae Park , Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
SangMin Shim , Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Soo-Mook Moon , Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
pp. 104

Tuning compiler optimizations for simultaneous multithreading (Abstract)

S.J. Eggers , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
D.M. Tullsen , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
J.L. Lo , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
S.S. Parekh , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
H.M. Levy , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 114

Exploiting Dead Value Information (Abstract)

Milo M. Martin , University of Wisconsin
Charles N. Fischer , University of Wisconsin
Amir Roth , University of Wisconsin
pp. 125
Session 4: Novel Microarchitectures: Chair: Ilan Spillinger, Intel

Trace Processors (Abstract)

Quinn Jacobson , University of Wisconsin - Madison
Yiannakis Sazeides , University of Wisconsin - Madison
Jim Smith , University of Wisconsin - Madison
Eric Rotenberg , University of Wisconsin - Madison
pp. 138

The Multicluster Architecture: Reducing Cycle Time Through Partitioning (Abstract)

Keith I. Farkas , Digital Equipment Corporation Western Research Lab
Zvonko Vranesic , Electrical and Computer Engineering University of Toronto
Paul Chow , Electrical and Computer Engineering University of Toronto
Norman P. Jouppi , Digital Equipment Corporation Western Research Lab
pp. 149

Out-of-Order Vector Architectures (Abstract)

James E Smith , University of Wisconsin-Madison
Roger Espasa , U. Politecnica de Catalunya-Barcelona
Mateo Valero , U. Politecnica de Catalunya-Barcelona
pp. 160
Session 5: Memory for Embedded Processors: Chair: Andrew Wolfe, Princeton University

The filter cache: an energy efficient memory structure (Abstract)

J. Kin , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Munish Gupta , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
W.H. Mangione-Smith , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 184

Improving Code Density Using Compression Techniques (Abstract)

I-Cheng Chen , University of Michigan
Charles Lefurgy , University of Michigan
Peter Bird , University of Michigan
Trevor Mudge , University of Michigan
pp. 194

Procedure based program compression (Abstract)

D. Kirovski , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Kin , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
W.H. Mangione-Smith , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 204
Session 6: Load/Store Tuning: Chair: Dean Tullsen, University of California, San Diego

Improving the accuracy and performance of memory communication through renaming (Abstract)

T.M. Austin , Michigan Univ., Ann Arbor, MI, USA
G.S. Tyson , Michigan Univ., Ann Arbor, MI, USA
pp. 218

Microarchitecture support for improving the performance of load target prediction (Abstract)

Chung-Ho Chen , Dept. of Electron. Eng, Nat. Yunlin Univ. of Sci. & Technol., Taiwan
A. Wu , Dept. of Electron. Eng, Nat. Yunlin Univ. of Sci. & Technol., Taiwan
pp. 228

Streamlining inter-operation memory communication via data dependence prediction (Abstract)

A. Moshovos , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
G.S. Sohi , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 235
Session 7: Value Prediction: Chair: Nancy Warter-Perez, California State University, Los Angeles

The Predictability of Data Values (Abstract)

James E. Smith , University of Wisconsin-Madison
Yiannakis Sazeides , University of Wisconsin-Madison
pp. 248

Value Profiling (Abstract)

Brad Calder , University of California, San Diego
Peter Feller , University of California, San Diego
Alan Eustace , Digital Equipment Corporation - WRL
pp. 259

Can Program Profiling Support Value Prediction? (Abstract)

Avi Mendelson , Technion - Israel Institute of Technology
Freddy Gabbay , Technion - Israel Institute of Technology
pp. 270

Highly Accurate Data Value Prediction using Hybrid Predictors (Abstract)

Manoj Franklin , Clemson University
Kai Wang , Datastream Systems, Inc.
pp. 281
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard

ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors (Abstract)

William E. Weihl , Digital Equipment Corporation
James E. Hicks , Digital Equipment Corporation
Jeffrey Dean , Digital Equipment Corporation
Carl A. Waldspurger , Digital Equipment Corporation
George Chrysos , Digital Equipment Corporation
pp. 292

Procedure Placement Using Temporal Ordering Information (Abstract)

Brad Calder , University of California, San Diego
Trevor Blackwell , Harvard University
Nikolas Gloy , Harvard University
Michael D. Smith , Harvard University
pp. 303

Available parallelism in video applications (Abstract)

Heng Liao , Princeton Univ., NJ, USA
A. Wolfe , Princeton Univ., NJ, USA
pp. 321

MediaBench: a tool for evaluating and synthesizing multimedia and communications systems (Abstract)

M. Potkonjak , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Chunho Lee , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
W.H. Mangione-Smith , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 330
Session 9: ILP Compiler Techniques II: Chair: Scott Mahlke, Hewlett-Packard

Cache Sensitive Modulo Scheduling (Abstract)

Antonio Gonzalez , Universitat Politecnica de Catalunya
F. Jesus Sanchez , Universitat Politecnica de Catalunya
pp. 338

Unroll-and-Jam Using Uniformly Generated Sets (Abstract)

Steve Carr , Michigan Technological University
Yiping Guan , Shafi Inc.
pp. 349

Resource-sensitive profile-directed data flow analysis for code optimization (Abstract)

Rajiv Gupta , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
J.Z. Fang , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
D.A. Berson , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 358

Author Index (PDF)

pp. 369
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