The Community for Technology Leaders
Proceedings of MICRO'95: 28th Annual IEEE/ACM International Symposium on Microarchitecture (1995)
Ann Arbor, MI, USA
Nov. 29, 1995 to Dec. 1, 1995
ISSN: 1072-4451
ISBN: 0-8186-7349-4
TABLE OF CONTENTS

[Front matter] (PDF)

pp. 3-14

Performance issues in correlated branch prediction schemes (Abstract)

N. Gloy , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
M.D. Smith , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
C. Young , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
pp. 3-14

Dynamic path-based branch correlation (Abstract)

R. Nair , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 15-23

The predictability of branches in libraries (Abstract)

B. Calder , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
D. Grunwald , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
pp. 24-34

The performance impact of incomplete bypassing in processor pipelines (Abstract)

P.S. Ahuja , Dept. of Comput. Sci., Princeton Univ., NJ, USA
D.W. Clark , Dept. of Comput. Sci., Princeton Univ., NJ, USA
A. Rogers , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 36-45

Critical path reduction for scalar programs (Abstract)

M. Schlansker , Hewlett-Packard Co., Palo Alto, CA, USA
V. Kathail , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 57-69

A limit study of local memory requirements using value reuse profiles (Abstract)

A.S. Huang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 71-81

Zero-cycle loads: microarchitecture support for reducing load latency (Abstract)

T.M. Austin , Wisconsin Univ., Madison, WI, USA
G.S. Sohi , Wisconsin Univ., Madison, WI, USA
pp. 82-92

A modified approach to data cache management (Abstract)

G. Tyson , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 93-103

Petri net versus module scheduling for software pipelining (Abstract)

V.H. Allan , Dept. of Comput. Sci., Utah State Univ., Logan, UT, USA
U.R. Shah , Dept. of Comput. Sci., Utah State Univ., Logan, UT, USA
K.M. Reddy , Dept. of Comput. Sci., Utah State Univ., Logan, UT, USA
pp. 105-110

Modulo scheduling with multiple initiation intervals (Abstract)

N.J. Warter-Perez , Dept. of Electr. & Comput. Eng., California State Univ., Los Angeles, CA, USA
N. Partamian , Dept. of Electr. & Comput. Eng., California State Univ., Los Angeles, CA, USA
pp. 111-118

Spill-free parallel scheduling of basic blocks (Abstract)

B. Natarajan , Hewlett-Packard Co., Palo Alto, CA, USA
M. Schlansker , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 119-124

Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation (Abstract)

J.W. Davidson , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
S. Jinturkar , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 125-132

Self-regulation of workload in the Manchester Data-Flow Computer (Abstract)

J.R. Gurd , Dept. of Comput. Sci., Manchester Univ., UK
D.F. Snelling , Dept. of Comput. Sci., Manchester Univ., UK
pp. 135-145

The M-Machine multicomputer (Abstract)

M. Fillo , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
S.W. Keckler , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
W.J. Dally , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
N.P. Carter , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
A. Chang , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
Y. Gurevich , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
W.S. Lee , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 146-156

Region-based compilation: an introduction and motivation (Abstract)

R.E. Hank , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 158-168

Register allocation for predicated code (Abstract)

A.E. Eichenberger , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 180-191

Partial resolution in branch target buffers (Abstract)

B. Fagin , Dept. of Comput. Sci., US Air Force Acad., USA
pp. 193-198

A system level perspective on branch architecture performance (Abstract)

B. Calder , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
D. Grunwald , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
pp. 199-206

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures (Abstract)

T.M. Conte , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
S.W. Sathaye , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 208-218

Improving CISC instruction decoding performance using a fill unit (Abstract)

M. Smotherman , Dept. of Comput. Sci., Clemson Univ., SC, USA
pp. 219-229

SPAID: software prefetching in pointer- and call-intensive environments (Abstract)

M.H. Lipasti , IBM Corp., Rochester, MN, USA
W.J. Schmidt , IBM Corp., Rochester, MN, USA
S.R. Kunkel , IBM Corp., Rochester, MN, USA
R.R. Roediger , IBM Corp., Rochester, MN, USA
pp. 231-236

An effective programmable prefetch engine for on-chip caches (Abstract)

Tien-Fu Chen , Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 237-242

Cache miss heuristics and preloading techniques for general-purpose programs (Abstract)

T. Ozawa , Fujitsu Labs. Ltd., Kawasaki, Japan
Y. Kimura , Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 243-248

Alternative implementations of hybrid branch predictors (Abstract)

Po-Yung Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E. Hao , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Y.N. Patt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 252-257

Control flow prediction with tree-like subgraphs for superscalar processors (Abstract)

S. Dutta , Semicond. Group, Texas Instrum. Inc., Dallas, TX, USA
pp. 258-263

The role of adaptivity in two-level adaptive branch prediction (Abstract)

S. Sechrest , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Chih-Chieh Lee , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 264-269

Design of storage hierarchy in multithreaded architectures (Abstract)

L. Roh , Div. of Math. & Comput. Sci., Argonne Nat. Lab., IL, USA
pp. 271-278

An investigation of the performance of various instruction-issue buffer topologies (Abstract)

S. Jourdan , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
P. Sainrat , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
D. Litaize , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
pp. 279-284

Decoupling integer execution in superscalar processors (Abstract)

S. Palacharla , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 285-290

Exploiting short-lived variables in superscalar processors (Abstract)

L.A. Lozano , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
G.R. Gao , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
pp. 292-302

Partitioned register file for TTAs (Abstract)

J. Janssen , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 303-312

Disjoint eager execution: an optimal form of speculative execution (Abstract)

A.K. Uht , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
V. Sindagi , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
K. Hall , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 313-325

Unrolling-based optimizations for modulo scheduling (Abstract)

D.M. Lavery , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.-W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 327-337

Stage scheduling: a technique to reduce the register requirements of a module schedule (Abstract)

A.E. Eichenberger , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 338-349

Hypernode reduction modulo scheduling (Abstract)

J. Llosa , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
E. Ayguade , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
A. Gonzalez , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 350-360
81 ms
(Ver 3.3 (11022016))