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Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture (1994)
San Jose, CA, USA
Nov. 30, 1994 to Dec. 2, 1994
ISSN: 1072-4451
ISBN: 0-89791-707-3
TABLE OF CONTENTS

Static branch frequency and program profile analysis (PDF)

Youfeng Wu , Sequent Comput. Syst., Beaverton, OR, USA
pp. 1-11

Using branch handling hardware to support profile-driven optimization (Abstract)

T.M. Conte , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
B.A. Patel , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 12-21

Branch classification: a new mechanism for improving branch predictor performance (PDF)

Po-Yung Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E. Hao , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 22-31

Techniques for compressing program address traces (Abstract)

A.R. Pleszkun , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 32-39

Height reduction of control recurrences for ILP processors (Abstract)

M. Schlansker , Hewlett-Packard Co., Palo Alto, CA, USA
V. Kathail , Hewlett-Packard Co., Palo Alto, CA, USA
S. Anik , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 40-51

Theoretical modeling of superscalar processor performance (Abstract)

D.B. Noonburg , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 52-62

Minimum register requirements for a module schedule (PDF)

A.E. Eichenberger , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 75-84

Minimizing register requirements under resource-constrained rate-optimal software pipelining (Abstract)

R. Govindarajan , Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John's, Nfld., Canada
pp. 85-94

Software pipelining with register allocation and spilling (PDF)

Jian Wang , Inst. fur Computersprachen, Tech. Univ. Wien, Austria
A. Krall , Inst. fur Computersprachen, Tech. Univ. Wien, Austria
M. Anton Ertl , Inst. fur Computersprachen, Tech. Univ. Wien, Austria
pp. 95-99

Reducing memory traffic with CRegs (Abstract)

P. Dahl , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
M. O'Keefe , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 100-104

Dynamic memory disambiguation for array references (Abstract)

D. Bernstein , IBM Haifa Res. Lab., Israel
D. Cohen , IBM Haifa Res. Lab., Israel
pp. 105-111

Data relocation and prefetching for programs with large data sets (Abstract)

Y. Yamada , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J. Gyllenhall , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
G. Haab , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Wen-Mei Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 118-127

Cache designs with partial address matching (PDF)

Lishing Liu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 128-136

Minimizing branch misprediction penalties for superpipelined processors (PDF)

Ching-Long Su , Adv. Comput. Archit. Lab., Univ. of Southern California, Los Angeles, CA, USA
A.M. Despain , Adv. Comput. Archit. Lab., Univ. of Southern California, Los Angeles, CA, USA
pp. 138-142

Facilitating superscalar processing via a combined static/dynamic register renaming scheme (Abstract)

E. Sprangle , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Y. Patt , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 143-147

Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution (Abstract)

R. Lo , MIPS Technol. Inc., Mountain View, CA, USA
Sun Chan , MIPS Technol. Inc., Mountain View, CA, USA
F. Chow , MIPS Technol. Inc., Mountain View, CA, USA
Shin-Ming Liu , MIPS Technol. Inc., Mountain View, CA, USA
pp. 148-152

A comparison of two pipeline organizations (Abstract)

M. Golden , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 153-161

A fill-unit approach to multiple instruction issue (Abstract)

M. Franklin , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 162-171

A high-performance microarchitecture with hardware-programmable functional units (Abstract)

R. Razdan , Harvard Univ., Cambridge, MA, USA
M.D. Smith , Harvard Univ., Cambridge, MA, USA
pp. 172-180

The anatomy of the register file in a multiscalar processor (Abstract)

S.E. Breach , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
T.N. Vijaykumar , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
G.S. Sohi , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 181-190

Register file port requirements of transport triggered architectures (Abstract)

J. Hoogerbrugge , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
H. Corporaal , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 191-195

The effects of predicated execution on branch prediction (Abstract)

G.S. Tyson , Dept. of Comput. Sci., California Univ., Davis, CA, USA
pp. 196-206

Characterizing the impact of predicated execution on branch prediction (Abstract)

S.A. Mahlke , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
R.E. Hank , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
R.A. Bringmann , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.C. Gyllenhaal , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
D.M. Gallagher , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.-M.W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 217-227

The effect of speculative updating branch history on branch prediction accuracy, revisited (PDF)

E. Hao , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Po-Yung Chang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Y.N. Patt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 228-232
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