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Proceedings of 26th Annual International Symposium on Microarchitecture (Cat. No.93TH0602-3) (1993)
Austin, TX, USA
Dec. 1, 1993 to Dec. 3, 1993
ISBN: 0-8186-5280-2
TABLE OF CONTENTS

Efficient scheduling of fine grain parallelism in loops (Abstract)

M. Rajagopalan , Department of Computer Science, Utah State University, Logan, Utah
V. H. Allan , Department of Computer Science, Utah State University, Logan, Utah
pp. 2-11

Employing finite automata for resource scheduling (Abstract)

Thomas Müller , GMD Forschungsstelle an der Universität Karlsruhe, Vincenz-Prieβnitz-Str. 1, D-76131 Karlsruhe, Germany
pp. 12-20

GPMB—software pipelining branch-intensive loops (Abstract)

Zhihong Tang , Dept. of Computer Science, Tsinghua University, Beijing 100084, China
Gang Chen , Dept. of Computer Science, Tsinghua University, Beijing 100084, China
Chihong Zhang , Dept. of Computer Science, Tsinghua University, Beijing 100084, China
Bogong Su , Dept. of Computer Science, The College of Staten Island, The City University of New York, Staten Island, NY
Stanley Habib , Computer Science Dept., The Graduate School and University Center, The City University of New York, 33 W. 42 St., New York, NY
pp. 21-30

A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus (Abstract)

Tim Stanley , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Michael Upton , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Patrick Sherhart , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Trevor Mudge , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Richard Brown , Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
pp. 31-40

Two-ported cache alternatives for superscalar processors (Abstract)

Andrew Wolfe , Department of Electrical Engineering, Princeton University
Rodney Boleyn , Department of Electrical Engineering, Princeton University
pp. 41-48

A study on the number of memory ports in multiple instruction issue machines (Abstract)

Soo-Mook Moon , IBM T.J. Watson Research Center, Hewlett-Packard Company, 11000 Wolfe Road, MS42U5, Cupertino, CA
Kemal Ebcioğlu , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY
pp. 49-59

The 16-fold way: a microparallel taxonomy (Abstract)

Barton J. Sano , Advanced Computer Architecture Laboratory, University of Southern California, Los Angeles
Alvin M. Despain , Advanced Computer Architecture Laboratory, University of Southern California, Los Angeles
pp. 60-69

A comparative performance evaluation of various state maintenance mechanisms (Abstract)

Michael Butler , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Yale Patt , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
pp. 70-79

Dynamically scheduled VLIW processors (Abstract)

B. Ramakrishna Rau , Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA
pp. 80-92

Prophetic branches: a branch architecture for code compaction and efficient execution (Abstract)

Apoorv Srivastava , Department of Computer Engineering, University of Southern California
Alvin M. Despain , Department of Computer Engineering, University of Southern California
pp. 94-99

A comparision of superscalar and decoupled access/execute architectures (Abstract)

Matthew K. Farrens , Department of Computer Science, University of California - Davis, Davis, CA
Pius Ng , Department of Computer Science, University of California - Davis, Davis, CA
Phil Nico , Department of Computer Science, University of California - Davis, Davis, CA
pp. 100-103

Measuring limits of parallelism and characterizing its vulnerability to resource constraints (Abstract)

Lawrence Rauchwerger , Center for Supercomputing R.&D., University of Illinois, 422 CSRL, 1308 W. Main St., Urbana, IL
Pradeep K. Dubey , T. J. Watson Research Center, I.B.M., P.O. Box 704, Yorktown Heights, NY
Ravi Nair , T. J. Watson Research Center, I.B.M., P.O. Box 704, Yorktown Heights, NY
pp. 105-117

An evaluation of bottom-up and top-down thread generation techniques (Abstract)

A. P. W. Böhm , Computer Science Department, Colorado State University, Fort Collins, CO
W. A. Najjar , Computer Science Department, Colorado State University, Fort Collins, CO
B. Shankar , Computer Science Department, Colorado State University, Fort Collins, CO
L. Roh , Computer Science Department, Colorado State University, Fort Collins, CO
pp. 118-127

Techniques for extracting instruction level parallelism on MIMD architectures (Abstract)

Gary Tyson , Computer Science Department, University of California, Davis, Davis, CA
Matthew Farrens , Computer Science Department, University of California, Davis, Davis, CA
pp. 128-137

Predictability of load/store instruction latencies (Abstract)

Santosh G. Abraham , EECS Department, The University of Michigan, Ann Arbor, MI
Rabin A. Sugumar , EECS Department, The University of Michigan, Ann Arbor, MI and Cray Research, Eau Claire, WI
Daniel Windheiser , Cray Research, Eau Claire, WI, EECS Department, The University of Michigan, Ann Arbor, MI
B. R. Rau , Hewlett Packard Laboratories, 1501 Page Mill Road, Bldg. 3U-7, Palo Alto, CA
Rajiv Gupta , Hewlett Packard Laboratories, 1501 Page Mill Road, Bldg. 3U-7, Palo Alto, CA
pp. 139-152

Control flow prediction for dynamic ILP processors (Abstract)

Dionisios N. Pnevmatikatos , Computer Sciences Department, University of Wisconsin-Madison, Madison, WI
Manoj Franklin , ECE Department, Clemson University, Clemson, SC
Gurindar S. Sohi , Computer Sciences Department, University of Wisconsin-Madison, Madison, WI
pp. 153-163

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors (Abstract)

Tse-Yu Yeh , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Yale N. Patt , Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
pp. 164-175

Clocked and asynchronous instruction pipelines (Abstract)

Mark A. Franklin , Computer and Communication Research Center, Washington University, St. Louis, MO
Tienyo Pan , Computer and Communication Research Center, Washington University, St. Louis, MO
pp. 177-184

An analysis of dynamic scheduling techniques for symbolic applications (Abstract)

Alessandra Costa , University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Alessandro De Gloria , University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Paolo Faraboschi , University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Mauro Olivieri , University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
pp. 185-191

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines (Abstract)

Nathalie Drach , IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
André Seznec , IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
pp. 193-201

Register renaming and dynamic speculation: an alternative approach (Abstract)

Mayan Moudgill , Department of Computer Science, Cornell University, Ithaca, NY
Keshav Pingali , Department of Computer Science, Cornell University, Ithaca, NY
Stamatis Vassiliadis , School of Electrical Engineering, Cornell University, Ithaca, NY and IBM Corporation, Enterprise Systems, Poughkeepsie, NY
pp. 202-213

Speculative execution exception recovery using write-back suppression (Abstract)

Roger A. Bringmann , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Scott A. Mahlke , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Richard E. Hank , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
John C. Gyllenhaal , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Wen-mei W. Hwu , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 214-223

EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors (Abstract)

Trung A. Diep , Computing Systems Center, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
John P. Shen , Computing Systems Center, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Mike Phillip , RISC Microprocessor Division, Motorola, Inc., 6501 William Cannon Drive West, Austin, Texas
pp. 225-235

An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors (Abstract)

Ing-Jer Huang , Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
Alvin M. Despain , Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
pp. 236-246

Superblock formation using static program analysis (Abstract)

Richard E. Hank , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Scott A. Mahlke , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Roger A. Bringmann , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
John C. Gyllenhaal , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Wen-mei W. Hwu , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 247-255

Instruction scheduling for the Motorola 88110 (Abstract)

Mark Smotherman , Department of Computer Science, Clemson University, Clemson, SC
Shuchi Chawla , Department of Computer Science, Clemson University, Clemson, SC
Stan Cox , Department of Computer Science, Clemson University, Clemson, SC
Brian Malloy , Department of Computer Science, Clemson University, Clemson, SC
pp. 257-262

A VLIW architecture based on shifting register files (Abstract)

H. Fatih Uğurdağ , General Motors NAO R&D Center in Warren, MI and Department of Computer Engineering and Science, Case Western Reserve University, Cleveland, Ohio
Christos A. Papachristou , Department of Computer Engineering and Science, Case Western Reserve University, Cleveland, Ohio
pp. 263-268
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