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Formal Methods and Models for Co-Design, ACM/IEEE International Conference on (2006)
Napa, CA USA
July 27, 2006 to July 30, 2006
ISBN: 1-4244-0421-5
pp: 93-102
W. Ecker , Infineon Technol. AG, Neubiberg, Germany
ABSTRACT
Electronic system level (ESL) reflects the current trend in hardware design and verification towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the abstraction level leads to reduced complexity compared to classical RTL modeling; however, due to this lack of detail, verification of higher level models produces new problems. Assertion based verification (ABV) - a well established RTL methodology - is a good example of this. Temporal relations in RTL properties are specified in terms of clocks that trigger the design. It is not obvious how to specify properties for more abstract, non-clocked models where the notion of lime is annotated as estimated delay values or omitted completely. Since ABV has already shown to be a strong methodology for functional RTL verification, we expect the same benefit for TL by lifting current ABV approaches to a higher level. In this paper we present a prototypic formal framework for specifying TL properties. We focus our work on three TL model views, as defined in the OSCI TLM standard. For each view we describe the model of computation and derive the required operators. Furthermore, we explain the required execution semantics and give some application examples
INDEX TERMS
Computational modeling, Timing, Clocks, Delay estimation, Hardware, Delay effects, Prototypes, Process design, System-level design, Runtime
CITATION

W. Ecker, V. Esen and M. Hull, "Execution semantics and formalisms for multi-abstraction TLM assertions," Formal Methods and Models for Co-Design, ACM/IEEE International Conference on(MEMCOD), Napa, CA USA, 2009, pp. 93-102.
doi:10.1109/MEMCOD.2006.1695910
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