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2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (2010)
Miami Beach, FL
Aug. 17, 2010 to Aug. 19, 2010
ISSN: 1526-7539
ISBN: 978-1-4244-8181-1
pp: 89-98
ABSTRACT
We propose a prefetch cache sizing module for use with any sequential prefetching scheme and evaluate its impact on the hit rate. Disk array caches perform sequential prefetching by loading data contiguous to I/O request data into the array cache. If the I/O workload has sequential locality, then data prefetched in response to sequential accesses in the workload will receive hits. Different schemes prefetch different data, so the prefetch cache size requirement varies. Moreover, the proportion of sequential and random requests in the workload and their interleaving pattern affects the size requirement. If the cache is too small, then prefetched data would get evicted from the cache before a request for the data arrives, thus lowering the hit rate. If the cache is too large, then valuable cache space is wasted. We present a simple sizing module that can be added to any prefetching scheme to ensure that the prefetch cache size is adequately matched to the requirement of the prefetching scheme on a dynamic workload comprising multiple streams. We analytically compute the maximal hit rate achievable by popular prefetching schemes and through simulations, show that our sizing module maintains the prefetch cache at a size that nearly achieves this maximal hit rate.
INDEX TERMS
cache storage, disc storage, interleaved storage
CITATION

S. Bhatia, E. Varki and A. Merchant, "Sequential Prefetch Cache Sizing for Maximal Hit Rate," 2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems(MASCOTS), Miami, Florida, 2010, pp. 89-98.
doi:10.1109/MASCOTS.2010.18
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