The Community for Technology Leaders
2013 14th Latin American Test Workshop - LATW (2012)
Quito, Ecuador Ecuador
Apr. 10, 2012 to Apr. 13, 2012
ISBN: 978-1-4673-2355-0
TABLE OF CONTENTS
Papers

[Front cover] (Abstract)

pp. c1

Author index (Abstract)

pp. 1-6

Committees (Abstract)

pp. 1-3

[Copyright notice] (Abstract)

pp. 1

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test (Abstract)

Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Abdullah Mumtaz , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Sybille Hellebrand , Institute of Electrical Engineering and Information Technology, University of Paderborn, Germany
Alejandro Cook , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
pp. 1-4

Simulation of SET faults in a voltage controlled oscillator (Abstract)

Ricardo Reis , PGMicro / PPGC - Universidade Federal do Rio Grande do Sul, Porto Alegre - Brazil
Fernanda L. Kastensmidt , PGMicro / PPGC - Universidade Federal do Rio Grande do Sul, Porto Alegre - Brazil
Walter E. Calienes Bartra , PGMicro / PPGC - Universidade Federal do Rio Grande do Sul, Porto Alegre - Brazil
pp. 1-6

Low voltage testing for interconnect opens under process variations (Abstract)

Michel Renovell , LIRMM-Universite de Montpellier II, 161 rue Ada 34392, France
Victor Champac , Dept. of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics-INAOE, Puebla, Mexico
Jesus Moreno , Dept. of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics-INAOE, Puebla, Mexico
pp. 1-6

Low-power design under variation using error prevention and error tolerance (invited paper) (Abstract)

Saibal Mukhopadhyay , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA-30332
Minki Cho , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA-30332
Kwanyeob Chae , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA-30332
pp. 1-6

Variation-aware and self-healing design methodology for a system-on-chip (Abstract)

Byunghoo Jung , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Srikar Bhagavatula , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Jangjoon Lee , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
pp. 1-4

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis (Abstract)

Raimund Ubar , Tallinn University of Technology, Estonia
Maksim Jenihhin , Tallinn University of Technology, Estonia
Jaan Raik , Tallinn University of Technology, Estonia
Urmas Repinski , Tallinn University of Technology, Estonia
Hanno Hantson , Tallinn University of Technology, Estonia
pp. 1-6

Self-optimization of dense wireless sensor networks based on simulated annealing (Abstract)

Carlos Montez , UFSC - Universidade Federal de Santa Catarina, Florianópolis, Brazil
José Marcio Machado , DCCE - UNESP - Universidade Estadual Paulista, São José do Rio Preto, Brazil
Adriano Cansian , DCCE - UNESP - Universidade Estadual Paulista, São José do Rio Preto, Brazil
A.R. Pinto , DCCE - UNESP - Universidade Estadual Paulista, São José do Rio Preto, Brazil
pp. 1-6

Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy (Abstract)

F. Mailly , LIRMM - CNRS/Univ. Montpellier 2 -161 me Ada, 34392, France
F. Azais , LIRMM - CNRS/Univ. Montpellier 2 -161 me Ada, 34392, France
A.A. Rekik , LIRMM - CNRS/Univ. Montpellier 2 -161 me Ada, 34392, France
P. Nouet , LIRMM - CNRS/Univ. Montpellier 2 -161 me Ada, 34392, France
pp. 1-6

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM (Abstract)

F. Vargas , Electrical Engineering Dept., Catholic University - PUCRS, Porto Alegre, Brazil
L. Bolzani , Electrical Engineering Dept., Catholic University - PUCRS, Porto Alegre, Brazil
T. Copetti , Electrical Engineering Dept., Catholic University - PUCRS, Porto Alegre, Brazil
A. Ceratti , Electrical Engineering Dept., Catholic University - PUCRS, Porto Alegre, Brazil
pp. 1-6

Parametric DC and noise measurements in a unified test & characterization software tool framework (Abstract)

Rogelio Palomera , Electrical and Computer Engineering Department, University of Puerto Rico at Mayagüez, 00681-9000 - USA
Lucianne Millan , Electrical and Computer Engineering Department, University of Puerto Rico at Mayagüez, 00681-9000 - USA
Fan-Chi Hou , Analog Technology Development, Texas Instruments, Inc., Dallas, 75243 - USA
William Morales , Electrical and Computer Engineering Department, University of Puerto Rico at Mayagüez, 00681-9000 - USA
Manuel Jimenez , Electrical and Computer Engineering Department, University of Puerto Rico at Mayagüez, 00681-9000 - USA
Jose A. Rodriguez , Analog Technology Development, Texas Instruments, Inc., Dallas, 75243 - USA
pp. 1-6

Automatic generation of an FPGA based embedded test system for printed circuit board testing (Abstract)

H.-D. Wuttke , Integrated Communication Systems Group, Ilmenau University of Technology, Germany
S. Ostendorff , Integrated Communication Systems Group, Ilmenau University of Technology, Germany
J. SachBe , Integrated Communication Systems Group, Ilmenau University of Technology, Germany
J.-H. Meza Escobar , Integrated Communication Systems Group, Ilmenau University of Technology, Germany
pp. 1-6

Platform for automated HW/SW co-verification, testing and simulation of microprocessors (Abstract)

Milos Krstic , IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany
Rolf Kraemer , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
Aleksandar Simevski , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
pp. 1-5

About robustness of test patterns regarding multiple faults (Abstract)

Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, Estonia
Sergei Kostin , Department of Computer Engineering, Tallinn University of Technology, Estonia
Raimund Ubar , Department of Computer Engineering, Tallinn University of Technology, Estonia
pp. 1-6

Model-based design for wireless body sensor network nodes (Abstract)

David Atienza , Embedded Systems Laboratory (ESL), EPFL, Switzerland
Vincenzo Rana , Politecnico di Milano, Italy
Paolo Roberto Grassi , Politecnico di Milano, Italy
Nadia Khaled , Politecnico di Milano, Italy
Francisco Rincon , DACYA, Universidad Complutense de Madrid, Spain
Ivan Beretta , Embedded Systems Laboratory (ESL), EPFL, Switzerland
Donatella Sciuto , Politecnico di Milano, Italy
pp. 1-6

Fast and scalable temperature-driven floorplan design in 3D MPSoCs (Abstract)

Martino Ruggiero , EPFL, Lausanne, Switzerland
J. Ignacio Hidalgo , Complutense University, Madrid, Spain
Jose L. Risco , Complutense University, Madrid, Spain
Jose L. Ayala , Complutense University, Madrid, Spain
Alessandro Vicenzi , EPFL, Lausanne, Switzerland
Ignacio Arnaldo , Complutense University, Madrid, Spain
David Atienza , EPFL, Lausanne, Switzerland
pp. 1-6

Fast worst-case peak temperature evaluation for real-time applications on multi-core systems (Abstract)

Lothar Thiele , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Hoeseok Yang , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Iuliana Bacivarov , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Lars Schor , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
pp. 1-6

Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring (Abstract)

J-M. Portal , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopole de Chateau - Gombert, 13451 Cedex 20, France
K. Castellani-Coulie , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopole de Chateau - Gombert, 13451 Cedex 20, France
H. Aziza , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopole de Chateau - Gombert, 13451 Cedex 20, France
W. Rahajandraibe , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopole de Chateau - Gombert, 13451 Cedex 20, France
F. Haddad , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopole de Chateau - Gombert, 13451 Cedex 20, France
pp. 1-5

Acquiring real-time heating of cells in standard cell designs (Abstract)

Marta Rencz , Budapest University of Technology and Economics, Department of Electron Devices, Hungary 111
Andras Timar , Budapest University of Technology and Economics, Department of Electron Devices, Hungary 111
pp. 1-5

Simulation framework for multilevel power estimation and timing analysis of digital systems allowing the consideration of thermal effects (Abstract)

Andras Poppe , Budapest University of Technology and Economics, Department of Electron Devices, Hungary 1117
Gergely Nagy , Budapest University of Technology and Economics, Department of Electron Devices, Hungary 1117
pp. 1-5

PSL assertion checkers synthesis with ASM based HLS tool ABELITE (Abstract)

Valentin Tihhomirov , Department of Computer Engineering, Tallinn University of Technology, ESTONIA
Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, ESTONIA
Samary Baranov , School of Engineering, Bar Ilan University, Ramat Gan, ISRAEL
Maksim Jenihhin , Department of Computer Engineering, Tallinn University of Technology, ESTONIA
pp. 1-6

Retiming scan circuit to eliminate timing penalty (Abstract)

Vishwani D. Agrawal , Auburn University, Department of Electrical and Computer Engineering, AL 36849, USA
Ozgur Sinanoglu , New York University Abu Dhabi, Department of Computer Engineering, PO Box 129188, UAE
pp. 1-6

Investigation of a CMOS oscillator concept for particle detection and diagnosis (Abstract)

J-M. Portal , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopôle de Château - Gombert, 13451 Cedex 20, France
G. Micolau , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopôle de Château - Gombert, 13451 Cedex 20, France
W. Rahajandraibe , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopôle de Château - Gombert, 13451 Cedex 20, France
H. Aziza , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopôle de Château - Gombert, 13451 Cedex 20, France
K. Castellani-Coulie , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Technopôle de Château - Gombert, 13451 Cedex 20, France
pp. 1-5

SITARe: A simulation tool for analysis and diagnosis of radiation effects (Abstract)

J-M. Portal , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Teclinopôle de Château - Gombert, 13451 Cedex 20, France
H. Aziza , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Teclinopôle de Château - Gombert, 13451 Cedex 20, France
K. Castellani-Coulie , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Teclinopôle de Château - Gombert, 13451 Cedex 20, France
G. Micolau , IM2NP-UMR CNRS 7334 / Aix-Marseille University, IM2NP, IMT Teclinopôle de Château - Gombert, 13451 Cedex 20, France
pp. 1-5

Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers (Abstract)

Rafael G. Vaz , UFRGS - Porto Alegre, RS, Brazil
Marcelo S. Lubaszewski , UFRGS - Porto Alegre, RS, Brazil
Tiago R. Balen , UFRGS - Porto Alegre, RS, Brazil
Guilherme S. Cardoso , UFRGS - Porto Alegre, RS, Brazil
Odair L. Goncalez , UFRGS - Porto Alegre, RS, Brazil
pp. 1-6

SET susceptibility estimation of clock tree networks from layout extraction (Abstract)

Ricardo Reis , Instituto de Informática, PPGC, PGMICRO, UFRGS, Porto Alegre, Brazil
Jorge Tonfat , Instituto de Informática, PPGC, PGMICRO, UFRGS, Porto Alegre, Brazil
Fernanda Lima Kastensmidt , Instituto de Informática, PPGC, PGMICRO, UFRGS, Porto Alegre, Brazil
Raul Chipana , Instituto de Informática, PPGC, PGMICRO, UFRGS, Porto Alegre, Brazil
pp. 1-6

SEU fault-injection in VHDL-based processors: A case study (Abstract)

Raoul Velazco , Laboratoire TIMA, Institue National Polytechnique, Grenoble, France
Wassim Mansour , Laboratoire TIMA, Institue National Polytechnique, Grenoble, France
pp. 1-5

Configurable tool to protect processors against SEE by software-based detection techniques (Abstract)

Fernanda Lima Kastensmidt , Institute de Informática - PPGC - UFRGS, Porto Alegre, Brazil
Angelo Cardoso Lapolli , Institute de Informática - PPGC - UFRGS, Porto Alegre, Brazil
Raul Sergio Barth , Institute de Informática - PPGC - UFRGS, Porto Alegre, Brazil
Eduardo Chielle , Institute de Informática - PPGC - UFRGS, Porto Alegre, Brazil
pp. 1-6

MoDiVHA: A hierarchical strategy for distributed test assignment (Abstract)

Luis C. E. Bona , Department of Informatics, Federal University of Paraná (UFPR), PO Box 19081 - Curitiba, 81531-990 - Brazil
Elias P. Duarte , Department of Informatics, Federal University of Paraná (UFPR), PO Box 19081 - Curitiba, 81531-990 - Brazil
Jefferson Paulo Koppe , Department of Informatics, Federal University of Paraná (UFPR), PO Box 19081 - Curitiba, 81531-990 - Brazil
pp. 1-6

Detailed analysis of compilation options for robust software-based embedded systems (Abstract)

R. Leveugle , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Fálix Viallet - 38031 Cedex - FRANCE
S. Bergaoui , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Fálix Viallet - 38031 Cedex - FRANCE
A. Wecxsteen , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Fálix Viallet - 38031 Cedex - FRANCE
pp. 1-6

Selective hardening methodology for combinational logic (Abstract)

Jean-Francois Naviner , Institut TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46, rue Barrault, 75634 - Cedex 13, France
Lirida A. de B. Naviner , Institut TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46, rue Barrault, 75634 - Cedex 13, France
Samuel N. Pagliarini , Institut TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46, rue Barrault, 75634 - Cedex 13, France
pp. 1-6

Pattern-based injections in processors implemented on SRAM-based FPGAs (Abstract)

R. Leveugle , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - FRANCE
M. Ben Jrad , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - FRANCE
pp. 1-4

[Front cover] (PDF)

pp. c1
Papers

Technical reviewers (Abstract)

pp. 1
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