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2015 16th Latin-American Test Symposium (LATS) (2015)
Puerto Vallarta, Mexico
March 25, 2015 to March 27, 2015
ISBN: 978-1-4673-6710-3
TABLE OF CONTENTS

Message from the LATS2015 Chairs (PDF)

Victor Champac , INAOE, Mexico
Yervant Zorian , Synopsys, USA
Leticia Bolzani Pohls , PUCRS, Brazil
Vishwani Agrawal , Auburn University, USA
pp. 1

Efficient fault injection in QEMU (Abstract)

Davide Ferraretto , University of Verona, Italy
Graziano Pravadelli , University of Verona, Italy
pp. 1-6

Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs (Abstract)

Hiroyuki Yamauchi , Fukuoka Institute of Technology, Fukuoka, Japan
Worawit Somha , King Mongkut's Institute of Technology Ladkrabang, Bangkok, Thailand
pp. 1-6

Complex delay fault reasoning with sequential 7-valued algebra (Abstract)

Jaak Kousaar , Tallinn University of Technology, Tallinn, Estonia
Raimund Ubar , Tallinn University of Technology, Tallinn, Estonia
Igor Aleksejev , Tallinn University of Technology, Tallinn, Estonia
pp. 1-6

Test set generation almost for free using a run-time FPGA reconfiguration technique (Abstract)

Alexandra Kourfali , Ghent University, B-9000 Ghent, Belgium
Dirk Stroobandt , Ghent University, B-9000 Ghent, Belgium
pp. 1-6

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG (Abstract)

N. Palermo , Politecnico di Torino, ITALY
V. Tihhomirov , Tallinn University of Technology, ESTONIA
T.S. Copetti , Catholic University - PUCRS, Porto Alegre, BRAZIL
M. Jenihhin , Tallinn University of Technology, ESTONIA
J. Raik , Tallinn University of Technology, ESTONIA
S. Kostin , Tallinn University of Technology, ESTONIA
M. Gaudesi , Politecnico di Torino, ITALY
G. Squillero , Politecnico di Torino, ITALY
M. Sonza Reorda , Politecnico di Torino, ITALY
F. Vargas , Catholic University - PUCRS, Porto Alegre, BRAZIL
L. Bolzani Poehls , Catholic University - PUCRS, Porto Alegre, BRAZIL
pp. 1-6

An evolutionary approach for test program compaction (Abstract)

R. Cantoro , Politecnico di Torino, Torino, Italy
M. Gaudesi , Politecnico di Torino, Torino, Italy
E. Sanchez , Politecnico di Torino, Torino, Italy
P. Schiavone , Politecnico di Torino, Torino, Italy
G. Squillero , Politecnico di Torino, Torino, Italy
pp. 1-6

A digital technique for the evaluation of SSB phase noise of analog/RF signals (Abstract)

F. Azais , LIRMM, CNRS/Univ. Montpellier 2, 34392 Montpellier Cedex, France
S. David-Grignot , LIRMM, CNRS/Univ. Montpellier 2, 34392 Montpellier Cedex, France
L. Latorre , LIRMM, CNRS/Univ. Montpellier 2, 34392 Montpellier Cedex, France
F. Lefevre , NXP Semiconductors Caen, 14000 Caen, France
pp. 1-6

Single event effects in an analog SOI transconductor: a case study (Abstract)

Carlos Viale , Universidad Catolica de Cordoba, Cordoba, Argentina
Pablo Petrashin , Universidad Catolica de Cordoba, Cordoba, Argentina
Luis Toledo , Universidad Catolica de Cordoba, Cordoba, Argentina
Walter Lancioni , Universidad Catolica de Cordoba, Cordoba, Argentina
Carlos Vazquez , Universidad Catolica de Cordoba, Cordoba, Argentina
pp. 1-4

CMOS amplifier with self-correction offset for SerDes applications (Abstract)

Rigoberto Bracamontes-Salazar , Freescale Semiconductor, Guadalajara, Mexico
Esdras Juarez-Hernandez , Freescale Semiconductor, Guadalajara, Mexico
Federico Lobato-Lopez , Freescale Semiconductor, Guadalajara, Mexico
Esteban Martinez-Guerrero , Jesuit University at Guadalajara, 45604, Mexico
pp. 1-4

Improving logic obfuscation via logic cone analysis (Abstract)

Yu-Wei Lee , University of Texas, Austin, TX 78712
Nur A. Touba , University of Texas, Austin, TX 78712
pp. 1-6

Virtual reconfigurable scan-chains on FPGAs for optimized board test (Abstract)

Igor Aleksejev , Tallinn Univ. of Technology, Tallinn, Estonia
Sergei Devadze , Testonica Lab OU, Tallinn, Estonia
Artur Jutman , Testonica Lab OU, Tallinn, Estonia
Konstantin Shibin , Tallinn Univ. of Technology, Tallinn, Estonia
pp. 1-6

A controllable setup and propagation delay flip-flop design (Abstract)

Alexandro Giron-Allende , Freescale Semiconductor, Guadalajara, Mexico
Victor Avendano , Freescale Semiconductor, Guadalajara, Mexico
Esteban Martinez-Guerrero , ITESO-The Jesuit University of Guadalajara, Guadalajara, 45604, Mexico
pp. 1-5

SW-based transparent in-field memory testing (Abstract)

Paolo Bernardi , Politecnico di Torino, Italy
Lyl Ciganda , Politecnico di Torino, Italy
Matteo Sonza Reorda , Politecnico di Torino, Italy
Said Hamdioui , Delft University of Technology, The Netherlands
pp. 1-6

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments (Abstract)

Jimmy Tarrillo , Universidad de Ingenieria y Tecnologia - UTEC Lima, Peru
Jorge Tonfat , Universidade Federal do Rio Grande do Sul - UFRGS Porto Alegre, Brazil
Lucas Tambara , Universidade Federal do Rio Grande do Sul - UFRGS Porto Alegre, Brazil
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul - UFRGS Porto Alegre, Brazil
Ricardo Reis , Universidade Federal do Rio Grande do Sul - UFRGS Porto Alegre, Brazil
pp. 1-6

Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs (Abstract)

Sandeep Kumar Singh , NIT Arunachal Pradesh, Yupia, India
Abir J Mondal , NIT Arunachal Pradesh, Yupia, India
Alak Majumder , NIT Arunachal Pradesh, Yupia, India
pp. 1-6

Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability (Abstract)

Andres Gomez , National Institute for Astrophysics, Optics and Electronics (INAOE), Mexico
Victor Champac , National Institute for Astrophysics, Optics and Electronics (INAOE), Mexico
pp. 1-6

Adopting multi-valued logic for reduced pin-count testing (Abstract)

Baohu Li , Auburn University, Auburn, AL 36849, USA
Bei Zhang , Auburn University, Auburn, AL 36849, USA
Vishwani D. Agrawal , Auburn University, Auburn, AL 36849, USA
pp. 1-6

Design dependent SRAM PUF robustness analysis (Abstract)

Mafalda Cortez , Delft University of Technology, Delft, The Netherlands
Said Hamdioui , Delft University of Technology, Delft, The Netherlands
Ryoichi Ishihara , Delft University of Technology, Delft, The Netherlands
pp. 1-6

A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETs (Abstract)

Jailene Hernandez , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
Johan Castrillon , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
Manuel Jimenez , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
Angel De La Torre , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
Pedro Escalona , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
Rogelio Palomera , University of Puerto Rico, Mayaguez, Puerto Rico 00681-9000
pp. 1-4

FPGA redundancy recovery based on partial bitstreams for multiple partitions (Abstract)

Victor M. Goncalves Martins , Federal University of Santa Catarina, Santa Catarina - Brazil
Joao Gabriel Reis , Federal University of Santa Catarina, Santa Catarina - Brazil
Horacio C. C. Netoy , Electronic System Design and Automation - INESC-ID, Lisboa, Portugal
Eduardo Augusto Bezerra , Federal University of Santa Catarina, Santa Catarina - Brazil
pp. 1-4

Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver (Abstract)

W. Rahajandraibe , Aix Marseille University, Marseille, France
F. Haddad , Aix Marseille University, Marseille, France
H. Aziza , Aix Marseille University, Marseille, France
K. Castellani-Coulie , Aix Marseille University, Marseille, France
J.-M. Portal , Aix Marseille University, Marseille, France
pp. 1-4

NBTI-induced circuit aging optimization by protectability-aware gate replacement technique (Abstract)

Guimao Zhang , Hefei University of Technology, Hefei, China
Maoxiang Yi , Hefei University of Technology, Hefei, China
Yong Miao , Hefei University of Technology, Hefei, China
Dawen Xu , Hefei University of Technology, Hefei, China
Huaguo Liang , Hefei University of Technology, Hefei, China
pp. 1-4

Study of regression methodologies on analog circuit design (Abstract)

Ivick Guerra-Gomez , SEMTECH, Aguascalientes, 20115 Mexico
Trent McConaghy , Solido Design Automation, Saskatoon, Canada
E. Tlelo-Cuautle , INAOE, Puebla, 72840 Mexico
pp. 1-6

Rare event diagnosis by iterative failure region locating and elite learning sample selection (Abstract)

Hosoon Shin , University of California, Riverside, CA 92521
Sheldon X.-D. Tan , University of California, Riverside, CA 92521
Guoyong Shi , Shanghai Jiao Tong University, Shanghai, 200240, China
Esteban Tlelo-Cuautle , Optical and Electrics (INAOE), Puebla, Mexico
pp. 1-5

Fault conditions of a simple chaotic circuit under capacitor nonlinear effects (Abstract)

J.L. Bueno-Ruiz , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
C.A. Arriaga-Arriaga , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
R. Huerta-Barrera , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
G.V. Cruz-Dominguez , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
C.H. Pimentel-Romero , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
J.M. Munoz-Pacheco , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
L.C. Gomez-Pavon , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
O. Felix-Beltran , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
A. Luis-Ramos , Benemerita Universidad Autonoma de Puebla, Puebla, MEXICO
pp. 1-5

A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems (Abstract)

S. Müller , Brandenburg University of Technology, Cottbus, Germany
T. Koal , Brandenburg University of Technology, Cottbus, Germany
S. Scharoba , Brandenburg University of Technology, Cottbus, Germany
H.T. Vierhaus , Brandenburg University of Technology, Cottbus, Germany
M. Schölzel , IHP and University of Potsdam Frankfurt (Oder)/Potsdam, Germany
pp. 1-6

Considerations on application of selective hardening based on software fault tolerance techniques (Abstract)

Felipe Restrepo-Calle , Universidad Nacional de Colombia, Bogota, Colombia
Sergio Cuenca-Asensi , University of Alicante, Alicante, Spain
Antonio Martínez-Alvarez , University of Alicante, Alicante, Spain
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
pp. 1-6

Test compression for circuits with multiple scan chains (Abstract)

Ondrej Novak , Technical University in Liberec, Liberec, Czech Republic
Jiri Jenícek , Technical University in Liberec, Liberec, Czech Republic
Martin Rozkovec , Technical University in Liberec, Liberec, Czech Republic
pp. 1-6

"Safe" built-in test and tuning of boost converters using feedback loop perturbations (Abstract)

X. Wang , Georgia Institute of Technology
K. Blanchard , Texas Instruments
S. Estella , Texas Instruments
A. Chatterjee , Georgia Institute of Technology
pp. 1-6

A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults (Abstract)

Takanori Moriyasu , Oita University, Oita 870-1192, Japan
Satoshi Ohtake , Oita University, Oita 870-1192, Japan
pp. 1-6

Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment (Abstract)

K. Coulie-Castellani , Universite de Toulon, Marseille, France
W. Rahajandraibe , Universite de Toulon, Marseille, France
H. Aziza , Universite de Toulon, Marseille, France
J.-M. Portal , Universite de Toulon, Marseille, France
G. Micolau , Universite d'Avignon, Avignon, France
pp. 1-5

Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect (Abstract)

J. Rafael Del-rey , ITESO - The Jesuit University of Guadalajara, Tlaquepaque, Jalisco. Mexico
Zabdiel Brito-Brito , ITESO - The Jesuit University of Guadalajara, Tlaquepaque, Jalisco. Mexico
Jose E. Rayas-sanchez , ITESO ? The Jesuit University of Guadalajara
pp. 1-5

Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors (Abstract)

Joao Guilherme Mourao Melo , Universidade Federal de Minas Gerais, Belo Horizonte, Brazil
Frank Sill Torres , Universidade Federal de Minas Gerais, Belo Horizonte, Brazil
pp. 1-6

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell (Abstract)

Hector Villacorta , Optics and Electronics - INAOE, Mexico
Roberto Gomez , University of Sonora, Mexico
Sebastia Bota , University of Balearic Islands, Mallorca, Spain
Jaume Segura , University of Balearic Islands, Mallorca, Spain
Victor Champac , Optics and Electronics - INAOE, Mexico
pp. 1-6

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS (Abstract)

Raul Acosta Hernandez , Integrated Systems Technological Laboratory, Sao Paulo, Brazil
Marius Strum , University of Sao Paulo, Sao Paulo, Brazil
Wang Jiang Chau , University of Sao Paulo, Sao Paulo, Brazil
pp. 1-6

Estimation of dynamic current waveforms using pre-characterization of standard cells (Abstract)

Bharath Shivashankar , University of Maryland, Baltimore County
Michael Skaggs , University of Maryland, Baltimore County
Sushmita Kadiyala Rao , University of Maryland, Baltimore County
Ryan Robucci , University of Maryland, Baltimore County
Nilanjan Banerjee , University of Maryland, Baltimore County
Chintan Patel , University of Maryland, Baltimore County
pp. 1-6

Exemplar-based failure triage for regression design debugging (Abstract)

Zissis Poulos , University of Toronto, Toronto, Canada
Andreas Veneris , University of Toronto, Toronto, Canada
pp. 1-6

Using only redundant modules with approximate logic to reduce drastically area overhead in TMR (Abstract)

Iuri A. C. Gomes , Porto Alegre, Rio Grande do Sul, Brazil
Mayler Martins , Porto Alegre, Rio Grande do Sul, Brazil
Andre Reis , Porto Alegre, Rio Grande do Sul, Brazil
Fernanda Lima Kastensmidt , Porto Alegre, Rio Grande do Sul, Brazil
pp. 1-6

Fault-tolerance in FPGA focusing power reduction or performance enhancement (Abstract)

C. Leong , INESC-ID Lisboa, 1000-029 Lisboa, Portugal
J. Semiao , INESC-ID Lisboa, 1000-029 Lisboa, Portugal
M.B. Santos , INESC-ID Lisboa, 1000-029 Lisboa, Portugal
I.C. Teixeira , INESC-ID Lisboa, 1000-029 Lisboa, Portugal
J.P. Teixeira , INESC-ID Lisboa, 1000-029 Lisboa, Portugal
pp. 1-6

Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture (Abstract)

Ronaldo R. Ferreira , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Ernesto Sanchez , Politecnico di Torino, Turin, Italy
Jean da Rolt , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Gabrie L. Nazar , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Alvaro F. Moreira , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Matteo Sonza Reorda , Politecnico di Torino, Turin, Italy
pp. 1-6

NBTI-aware design of integrated circuits: a hardware-based approach (Abstract)

T. Copetti , PUCRS, Porto Alegre, Brazil
G. Cardoso Medeiros , PUCRS, Porto Alegre, Brazil
L. Bolzani Poehls , PUCRS, Porto Alegre, Brazil
F. Vargas , PUCRS, Porto Alegre, Brazil
pp. 1-6

Design of ultra-low-power smart wearable systems (Abstract)

Gregoire Surrel , Embedded Systems Laboratory (ESL), EPFL, Switzerland
Francisco Rincon , SmartCardia Sàrl. Switzerland
Srinivasan Murali , SmartCardia Sàrl. Switzerland
David Atienza , Embedded Systems Laboratory (ESL), EPFL, Switzerland
pp. 1-2
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