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2015 16th Latin-American Test Symposium (LATS) (2015)
Puerto Vallarta, Mexico
March 25, 2015 to March 27, 2015
ISBN: 978-1-4673-6710-3
pp: 1-6
Bharath Shivashankar , University of Maryland, Baltimore County
Michael Skaggs , University of Maryland, Baltimore County
Sushmita Kadiyala Rao , University of Maryland, Baltimore County
Ryan Robucci , University of Maryland, Baltimore County
Nilanjan Banerjee , University of Maryland, Baltimore County
Chintan Patel , University of Maryland, Baltimore County
ABSTRACT
Power supply noise is a critical issue in transition and delay testing. As compared to functional operations, test vectors induce increased switching. This escalation in switching contributes to an increase in power supply noise which, in turn, causes an increase in path delays. During testing, false positives due to excessive noise-induced failures negatively impacts yield. In our previous work, we implemented a modular framework to dynamically estimate power supply noise caused by simultaneous switching of multiple paths and the increase in path delay. In this technique, the design is partitioned into the logic and grid subsystems that are analyzed independently. The approach eliminated the need to run resource intensive full-chip SPICE simulations. Although independent logic path simulations provide a considerable time improvement in comparison to full-chip run time, in large designs, even these isolated path simulations can be prohibitive. In this paper, we present a novel technique to estimate the current transients of a path by precharacterizing each standard cell in the library to predict the variations in the power supply. This one time precharacterization has a significant advantage over our previously implemented technique since it no longer requires a full path simulation to estimate accurate current transients. Initial data presented in this paper show promising results.
INDEX TERMS
Logic gates, Delays, SPICE, Transient analysis, Standards, Power supplies, Noise
CITATION

B. Shivashankar, M. Skaggs, S. K. Rao, R. Robucci, N. Banerjee and C. Patel, "Estimation of dynamic current waveforms using pre-characterization of standard cells," 2015 16th Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, 2015, pp. 1-6.
doi:10.1109/LATW.2015.7102520
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