The Community for Technology Leaders
System-on-Chip for Real-Time Applications, International Workshop on (2005)
Banff, Alberta, Canada
July 20, 2005 to July 24, 2005
ISBN: 0-7695-2403-6
TABLE OF CONTENTS

Introduction (PDF)

pp. xii,xiii,xiv,xv,xvi
Plenary
Semiconductor Technologies

System-on-Chip Design beyond 50 GHz, invited (Abstract)

A. Mangan , University of Toronto
C. Lee , University of Toronto
T. Yao , University of Toronto
M. Gordon , University of Toronto
S. P. Voinigescu , University of Toronto
K. Yau , University of Toronto
pp. 10-13
Software/Hardware System Co-design

HW/SW Co-Design for SoC on Mobile Platforms, invited (Abstract)

Dieter Kasperkovitz , Semiconductor Ideas to the Market
Johan van der Tang , Eindhoven University of Technology and Semiconductor Ideas to the Market
Harm van Rumpt , Semiconductor Ideas to the Market
pp. 19-23

A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction (Abstract)

G. Bois , ?cole Polytechnique de Montr?al
E. M. Aboulhamid , Universit? de Montr?al
A. Tsikhanovich , Universit? de Montr?al
pp. 24-29

The Software/Hardware Co-Debug Environment with Emulator (Abstract)

Xuecheng Zou , Huazhong University of Science and Technology
Baodong Yu , Huazhong University of Science and Technology
pp. 34-38
Manufacturing & Reliability

DfM for SoC, invited (Abstract)

A. Balasinski , Cypress Semiconductor
pp. 41-46

ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited (Abstract)

Peter Bendix , Xpedion Design Systems/Global Technology Leader
Jau-Wen Chen , LSI Logic Corp.
Larry D. Johnson , LSI Logic Corp.
Yoon Huh , Global Technology Leader
Ravindra Narayan , LSI Logic Corp.
Steven H. Voldman , IBM Microelectronics
Kyungjin Min , Global Technology Leader
pp. 47-53

Leakage Current Variability in Nanometer Technologies, invited (Abstract)

Mohab Anis , University of Waterloo
Mohamed H. Aburahma , University of Waterloo
pp. 60-63
Memories for SoC

Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited (Abstract)

A. Maurelli , FTM Advanced R—D-NVMTD-STMicroelectronics
P. Pavan , University of Modena and Reggio Emilia
L. Larcher , University of Modena and Reggio Emilia
pp. 73-77

Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits (Abstract)

Dong-Shong Liang , Kun Shan University of Technology
Feng-Chang Chiang , Kun Shan University of Technology
Kwang-Jow Gan , Kun Shan University of Technology
Shih-Yu Wang , Kun Shan University of Technology
Yaw-Hwang Chen , Kun Shan University of Technology
Chung-Chih Hsiao , Kun Shan University of Technology
Shun-Huo Kuo , Kun Shan University of Technology
Long-Xian Su , Kun Shan University of Technology
Cher Shiung Tsai , Kun Shan University of Technology
Chi-Pin Chen , Kun Shan University of Technology
pp. 78-81
Analog and Mixed-Signal IC Design

PLL-Based Fractional-N Frequency Synthesizers (Abstract)

Farhad Zarkeshvari , Carleton University
Peter Noel , Carleton University
Tad Kwasniewski , Carleton University
pp. 85-91

A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling (Abstract)

Edward Gebara , Georgia Institute of Technology
Joy Laskar , Georgia Institute of Technology
Hyoungsoo Kim , Georgia Institute of Technology
Franklin Bien , Georgia Institute of Technology
Soumya Chandramouli , Georgia Institute of Technology
Youngsik Hur , Georgia Institute of Technology
Moonkyun Maeng , Georgia Institute of Technology
pp. 101-106

A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit (Abstract)

Wen-Ching Lee , National Kaohsiung First University of Science and Technology
Shih-Chang Hsia , National Kaohsiung First University of Science and Technology
pp. 107-110

Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation (Abstract)

Ke-Horng Chen , National Chiao-Tung University
Chia-Jung Chang , National Chiao-Tung University
pp. 111-116

Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications (Abstract)

Chi-Chieh Chuang , Kun Shan Universiv of Technology
Tsung-Tien Hou , Kun Shan Universiv of Technology
Hung-Yu Wang , National Applied Research Laboratorie
Chun-Yueh Huang , Kun Shan Universiv of Technology
pp. 117-122

A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture (Abstract)

Rabin Raut , Concordia University
Syed Masood Ali , Concordia University
Mohamad Sawan , Ecole Polytechnique Montreal
pp. 123-126

A Comprehensive Model for On-Chip Spiral Inductors (Abstract)

N. Masoumi , University of Tehran
B. Khadem Hosseinieh , University of Tehran
pp. 127-131

Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits (Abstract)

Krzysztof Iniewski , University of Alberta
James W. Haslett , University of Calgary
Kenneth A. Townsend , University of Calgary
pp. 132-136
Digital System Design for SoC

Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion (Abstract)

Robert Bogdan Staszewski , Texas Instruments Inc
Sameh Rezeq , Texas Instruments Inc
John Wallberg , Texas Instruments Inc
Chih-Ming Hung , Texas Instruments Inc
Patrick Cruise , Texas Instruments Inc
pp. 154-159

Improved Wideband Low Distortion Cascaded Delta-Sigma Modulator (Abstract)

Xiaobo Wu , Zhejiang University
Andreas Gothenberg , Zhejiang University
Xiaolong Yuan , Zhejiang University
pp. 160-164
Sensors

Noise Analysis of a CMOS Active Pixel Sensor for Tomographic Mammography (Abstract)

Karim S. Karim , Simon Fraser University
Mohammad Hadi Izadi , Simon Fraser University
pp. 167-171

A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor (Abstract)

Yanbin Wang , Carleton University
Yanjie Wang , University of Alberta
Kris Iniewski , University of Alberta
Garry Tarr , Carleton University
pp. 176-179

A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology (Abstract)

Haigang Yang , Chinese Academy of Sciences
Hongguang Sun , Chinese Academy of Sciences
Hua Zhong , Chinese Academy of Sciences
Shanhong Xia , Chinese Academy of Sciences
Jinghong Han , Chinese Academy of Sciences
Zengjin Lin , Chinese Academy of Sciences
Jinbao Wei , Chinese Academy of Sciences
pp. 180-183

A Very Low Power CMOS Potentiostat for Bioimplantable Applications (Abstract)

Graham A. Jullien , University of Calgary
Mohammad M. Ahmadi , University of Calgary
pp. 184-189
Multimedia IP Cores

An Acoustic Echo Canceller Chip (Abstract)

Vafa Sedghi , Soha Industrial Development
Mostafa Borhani , Soha Industrial Development
pp. 193-198

A High-Performance Error Concealment Processor for Video Decoder (Abstract)

Shih Wen Chou , National Kaohsiung First University of Science and Technology
Shih-Chang Hsia , National Kaohsiung First University of Science and Technology
pp. 199-202

A Scalable Low Power Imager Architecture for Compound-Eye Vision Sensors (Abstract)

Chen Shoushun , Hong Kong University of Science and Technology
Amine Bermak , Hong Kong University of Science and Technology
Farid Boussaid , University of Western Australia
pp. 203-206

UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC (Abstract)

Wael Badawy , University of Calgary
Choudhury A. Rahman , University of Calgary
pp. 207-210

A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4 (Abstract)

Ihab Amer , University of Calgary
Choudhury A. Rahman , University of Calgary
Tamer Mohamed , University of Calgary
Mohammed Sayed , University of Calgary
Wael Badawy , University of Calgary
pp. 211-214
Wireless Systems

Digital RF Processing Techniques for SoC Radios, invited (Abstract)

Dirk Leipold , Texas Instruments Inc.
Robert Bogdan Staszewski , Texas Instruments Inc.
Khurram Muhammad , Texas Instruments Inc.
pp. 217-222
Wireless Systems

VHDL Simulation and Modeling of an All-Digital RF Transmitter (Abstract)

Poras T. Balsara , University of Texas at Dallas
Robert Bogdan Staszewski , Texas Instruments
Roman Staszewski , Texas Instruments
pp. 233-238

A 2.3GHz CMOS Transimpedance Preamplifier for Optical Communication (Abstract)

Kris Iniewski , University of Alberta
Yanjie Wang , University of Alberta
pp. 243-246

A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz (Abstract)

Kris Iniewski , University of Alberta
M. Zamin Khan , Concordia University
Yanjie Wang , University of Alberta
pp. 247-251

A Tier 3 Software Defined AM Radio (Abstract)

Robert Hang , University of Alberta
Jung Ko , University of Alberta
Vincent C. Gaudet , University of Alberta
pp. 257-261
VLSI Physical Design

A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance (Abstract)

N. Masoumi , University of Tehran
C. Lucas , University of Tehran
S. A. Moghaddam , University of Tehran
pp. 265-269

A Structure Based Clustering Algorithm with Applications to VLSI Physical Design (Abstract)

Laleh Behjat , University of Calgary
Jianhua Li , University of Calgary
Blair Schiffner , University of Calgary
pp. 270-274

Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization (Abstract)

M. F. Anjos , University of Waterloo
A Vannelli , University of Waterloo
P. L. Takouda , University of Waterloo
pp. 275-280
Towards SoC Design Automation Tools for SoC

Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm (Abstract)

M. Ahmadian , K. N. Toosi University of Technology
F. Raissi , K. N. Toosi University of Technology
J. Ghasemi , University of Tehran
M. Masoumi , K. N. Toosi University of Technology
N. Masoumi , University of Tehran
pp. 283-288

Component-Based Methodology for Hardware Design of a Dataflow Processing Network (Abstract)

Robert Grou-Szabo , ?cole Polytechnique
Gabriela Nicolescu , ?cole Polytechnique
Yvon Savaria , ?cole Polytechnique
Hany Ghattas , ?cole Polytechnique
pp. 289-294

An Automatic Layout Generator for I/O Cells (Abstract)

Jing-Jou Tang , Southern Taiwan University of Technology
Mi-Chang Chang , Southern Taiwan University of Technology
Li-Chun Tien , Southern Taiwan University of Technology
pp. 295-300

Additional Knowledge of Bus Invert Coding Schemes (Abstract)

Tina Lindkvist , Linköpings Universitet
pp. 301-303

High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions (Abstract)

Massimo Ravasi , Swiss Federal Institute of Technology of Lausanne
Marco Mattavelli , Swiss Federal Institute of Technology of Lausanne
pp. 304-307

Practical Techniques for Performance Estimation of Processors (Abstract)

Abhijit Ray , Nanyang Technological University
Wu Jigang , Nanyang Technological University
Thambipillai Srikanthan , Nanyang Technological University
pp. 308-311

A Multivalue Eigenvalue Based Circuit Partitioning Technique (Abstract)

Jianhua Li , University of Calgary
Laleh Behjat , University of Calgary
Blair Schiffner , University of Calgary
pp. 312-316

A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms (Abstract)

Haidar Harmanani , Lebanese American University
Bassem Karablieh , Lebanese American University
pp. 317-322

Accelerating Functional Simulation for Processor Based Designs, invited (Abstract)

Russell Klein , Mentor Graphics Corporation
Tomasz Piekarz , Mentor Graphics Corporation
pp. 323-328

Instruction Based Testbench Architecture, invited (Abstract)

Sin-chong Park , Information and Communications University
Seung-beom Lee , Information and Communications University
Ho-seok Choi , Information and Communications University
pp. 329-333
Low-Power SoC

A Precise Model for Leakage Power Estimation in VLSI Circuits (Abstract)

Akbarzadeh , University of Tehran
S. Aghnoot , University of Tehran
J. Derakhshandeh , University of Tehran
B. Kasiri , University of Tehran
Y. Farazmand , University of Tehran
Nasser Masoumi , University of Tehran
pp. 337-340

Turbo Codes — Digital IC Design (Abstract)

Moeed Israr , Carleton University
Tad Kwasniewski , Carleton University
pp. 341-346

A Low Area and Low Power Programmable Baseband Processor Architecture (Abstract)

Dake Liu , Link?ping University
Eric Tell , Link?ping University
Anders Nilsson , Link?ping University
pp. 347-351

Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter (Abstract)

Kuo-Tai Chang , National Chiao Tung University
Ke-Horng Chen , National Chiao Tung University
Hung-Ch Lee , National Chiao Tung University
Wen Tsao Chen , National Chiao Tung University
pp. 352-357

An Optimal ILP Model for Delay Time to Minimize Peak Power and Area (Abstract)

Chi-Ho Lin , Semyung University
Ki-Bog Kim , Semyung University
pp. 358-362

Power Reduction Technique Using Multi-vt Libraries (Abstract)

Meeta Srivastav , Indian Institute of Technology at Bombay
Himanshu Bhatnagar , Conexant Systems
S. S. S. P. Rao , Indian Institute of Technology at Bombay
pp. 363-367

A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets (Abstract)

Ehsan Mirhadi , University of Waterloo
Payam Ghafari , University of Waterloo
Shawki Areibi , University of Waterloo
Mohamed Elmasry , University of Waterloo
Mohab Anis , University of Waterloo
pp. 368-371

Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits (Abstract)

Feng-Chang Chiang , Kun Shan University of Technology
Yaw-Hwang Chen , Kun Shan University of Technology
Shih-Yu Wang , Kun Shan University of Technology
Long-Xian Su , Kun Shan University of Technology
Chung-Chih Hsiao , Kun Shan University of Technology
Cher-Shiung Tsai , Kun Shan University of Technology
Shun-Huo Kuo , Kun Shan University of Technology
Dong-Shong Liang , Kun Shan University of Technology
Kwang-Jow Gan , Kun Shan University of Technology
pp. 372-375

An Area-Efficient High-Speed AES S-Box Method (Abstract)

Scott Wakelin , Simon Fraser University
Richard Hobson , Simon Fraser University
pp. 376-379

Low Latency and Power Efficient VD Using Register Exchanged State-Mapping Algorithm (Abstract)

Sang-Ho Seo , Information and Communications University
Sin-Chong Park , Information and Communications University
pp. 380-384
Digital IP Cores

A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier (Abstract)

Amir Khatibzadeh , University of Waterloo
Kaamran Raahemifar , Ryerson University
pp. 387-391

Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process (Abstract)

Feng-Chang Chiang , Kun Shan University of Technology
Dong-Shong Liang , Kun Shan University of Technology
Shih-Yu Wang , Kun Shan University of Technology
Yaw-Hwang Chen , Kun Shan University of Technology
Kwang-Jow Gan , Kun Shan University of Technology
Cher-Shiung Tsai , Kun Shan University of Technology
Chi-Pin Chen , Kun Shan University of Technology
Chung-Chih Hsiao , Kun Shan University of Technology
Shun-Huo Kuo , Kun Shan University of Technology
pp. 392-395

An Area-Reduced Scheme for Modulo 2ⁿ-1 Addition/Subtraction (Abstract)

Shaoqiang Bi , McGill University
Warren J. Gross , McGill University
M. N. S. Swamy , Concordia University
Wei Wang , Purdue University
Asim Al-Khalili , Concordia University
pp. 396-399

Very High Radix Scalable Montgomery Multipliers (Abstract)

David Harris , Harvey Mudd College
Kyle Kelley , Harvey Mudd College
pp. 400-404
Programmable and Reconfigurable Cores

Low-Power Programmable Signal Processing, invited (Abstract)

Paul Hasler , Georgia Institute of Technology
pp. 413-418

An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking (Abstract)

Mona Safar , Ain Shams University
Ashraf Salem , Mentor Graphics
M. Watheq El-Kharashi , University of Victoria
pp. 419-424

A Field-Programmable Analog Array Using Translinear Elements (Abstract)

David N. Abramson , Georgia Institute of Technology
Paul Hasler , Georgia Institute of Technology
Shyam Subramanian , Georgia Institute of Technology
Jordan D. Gray , Georgia Institute of Technology
pp. 425-428

System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array (Abstract)

Yiannos Manoli , University of Freiburg
Fabian Henrici , University of Freiburg
Joachim Becker , University of Freiburg
pp. 434-438

FPGA Implementation of Digital Controller for DC-DC Buck Converter (Abstract)

Miro Milanovic , University of Maribor and TECES
Mitja Truntic , University of Maribor
pp. 439-443

Systolic Array-Based String Matching Unit for Spam Blocking (Abstract)

Fayez Gebali , University of Victoria
M. Watheq El-Kharashi , University of Victoria
A. N. M. Ehtesham Rafiq , University of Victoria
pp. 444-449

An FPGA Design of a Unified Hash Engine for IPSec Authentication (Abstract)

Fayez Gebali , University of Victoria
Mostafa Abd-El-Barr , University of Victoria
Esam Khan , University of Victoria
M. Watheq El-Kharashi , University of Victoria
pp. 450-453

Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period (Abstract)

Bill Pontikakis , ?cole Polytechnique de Montr?al
Fran?ois-R. Boyer , ?cole Polytechnique de Montr?al
Yvon Savaria , ?cole Polytechnique de Montr?al
pp. 454-458

Programmable Low Dropout Voltage Regulator (Abstract)

Paul Hasler , Georgia Institute of Technology
AiChen Low , Georgia Institute of Technology
pp. 459-462
Emerging Issue

Three Dimensional System on Chip Technology, invited (Abstract)

Earl E. Swartzlander, Jr. , University of Texas at Austin
pp. 465-470

Simulation and Analysis of Network on Chip Architecture for Wireless Communication System (Abstract)

Sung-Rok Yoon , Information and Communications University
Sin-Chong Park , Information and Communications University
pp. 471-475

Recent Advances and Future Trends in Low Power Wireless Systems for Medical Applications (Abstract)

Mourad N. El-Gamal , McGill University
Kenneth A. Townsend , University of Calgary
James W. Haslett , University of Calgary
Tommy K. K. Tsang , McGill University
Krzysztof Iniewski , University of Alberta
pp. 476-481

Floating-Gate Devices, Circuits, and Systems, invited (Abstract)

Paul Hasler , Georgia Institute of Technology
pp. 482-487
IP-Blocks for Broadband Networking

10 GBPS over Copper Lines — State of the Art in VLSI, invited (Abstract)

Stephen Bates , University of Alberta
Kris Iniewski , University of Alberta
pp. 491-494

Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications (Abstract)

Tad Kwasniewski , Carleton University
Shoujun Wang , Altera Corporation
Peter Noel , Carleton University
Miao Li , Carleton University
pp. 500-502

A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications (Abstract)

Jen-Ming Wu , National Tsing Hua University
Hou-Cheng Tzeng , National Tsing Hua University
Yu-Ho Hsu , National Tsing Hua University
Chun-Chieh Chang , National Tsing Hua University
Ching-Te Chiu , National Tsing Hua University
Kai-Ming Feng , National Tsing Hua University
Ming-Chang Du , National Tsing Hua University
Shih-Min Chen , National Tsing Hua University
pp. 508-513
MPSOC

Synchronous Pipelined Relay Stations with Back-Pressure Tolerance (Abstract)

Raman Mittal , University of Southern California
Roger Su , University of Southern California
Vivek Garg , University of Southern California
pp. 517-520

Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator Controller (Abstract)

Xiqun Zhu , University of Maryland at College Park
Yuan Ma , University of Maryland at College Park
pp. 521-524

Architecture for Multi-processor SoC Platform Using Dedicated Channels (Abstract)

Sin-Chong Park , Information and Communications University
Gyongsu Lee , Information and Communications University
pp. 525-529

Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies (Abstract)

Shinwook Kang , Samsung Electronics Co., Ltd.
Sangik Choi , Samsung Electronics Co., Ltd.
pp. 530-534

Traffic Configuration for Evaluating Networks on Chips (Abstract)

Zhonghai Lu , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
pp. 535-540

Orthogonalized Communication Architecture for MP-SoC with Global Bus (Abstract)

Sin-Chong Park , Information and Communications University
Jin Lee , Information and Communications University
pp. 541-545

MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design (Abstract)

Luiza Gheorghe , Ecole Polytechnique de Montr?al
Gabriela Nicolescu , Ecole Polytechnique de Montr?al
pp. 546-551

Transaction Analysis of Multiprocessor Based Platform with Bus Matrix (Abstract)

Sin-Chong Park , Information and Communications University
Seungbeom Lee , Information and Communications University
pp. 552-556

A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs (Abstract)

Yvon Savaria , ?cole Polytechnique de Montr?al
Hung Tien Bui , ?cole Polytechnique de Montr?al
pp. 557-562
Author Index

Author Index (PDF)

pp. 563-565
101 ms
(Ver )