The Community for Technology Leaders
System-on-Chip for Real-Time Applications, International Workshop on (2004)
Banff, Alberta, Canada
July 19, 2004 to July 21, 2004
ISBN: 0-7695-2182-7
TABLE OF CONTENTS
Plenary Session

SoC Integration Challenges (PDF)

Russell Klein , Mentor Graphics
pp. 3
Tutorial 1
Tutorial 2

High-Speed I/Os and PLLs for Data Communication Applications (PDF)

Shahriar Mirabbasi , University of British Columbia
Krzysztof (Kris) Iniewski , University of Alberta
pp. 11-12
Tutorial 3
Nanometer SoC

Silicon Modeling of Nanometer Systems-on-Chip (Abstract)

Carey Robertson , Mentor Graphics Corp.
pp. 19-22
Sensor IP-Blocks

A Real-time Architecture of SOC Selective Gas Sensor Array Using KNN Based on the Dynamic Slope and the Steady State Response (Abstract)

Shi Minghua , Hong Kong University of Science and Technology
Amine Bermak , Hong Kong University of Science and Technology
Sofiane Brahim-Belhouari , Hong Kong University of Science and Technology
pp. 29-32

A Digital CMOS Imager with Pixel Level Analog-to-digital Converter and Reconfigurable SRAM/Counter (Abstract)

Amine Bermak , Hong Kong University of Science and Technology
Yat-Fong Yung , Hong Kong University of Science and Technology
pp. 33-36
Modeling and Simulation I

Interface-based Design of Systems-on-Chip using UML-RT (Abstract)

Alexandre Chureau , ?cole Polytechnique de Montr?al, Canada
El Mostapha Aboulhamid , Universit? de Montr?al, Canada
Yvon Savaria , ?cole Polytechnique de Montr?al, Canada
pp. 39-44

Using Design Patterns for Type Unification and Introspection in SystemC (Abstract)

Luc Charest , Universit? de Montr?al
El Mostapha Aboulhamid , Universit? de Montr?al
Guy Bois , ?cole Polytechnique de Montr?al
pp. 45-50

A Framework for Implementing Reusable Digital Signal Processing Modules (Abstract)

L-P. Lafrance , ?cole Polytechnique de Montr?al
Y. Savaria , ?cole Polytechnique de Montr?al
pp. 51-54
Advanced Arithmetic IP-Blocks

A Programmable Base MDLNS MAC with Self-Generated Look-Up Table (Abstract)

W. Zhang , University of Calgary, Canada
G. A. Jullien , University of Calgary, Canada
V. S. Dimitrov , University of Calgary, Canada
pp. 61-64

64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design (Abstract)

Kuo-Hsing Cheng , National Central University, Taiwan
Shun-Wen Cheng , tku, Taiwan
Chan-Wei Huang , National Central University, Taiwan
pp. 65-68

FPGA Implementation of Fast Radix 4 Division Algorithm (Abstract)

Hamed A. Elsimary , ERI, Cairo, Egypt
Attif A. Ibrahem , ERI, Cairo, Egypt
Aly E. Salama , Cairo University, Cairo, Egypt
pp. 69-72

CRT-Based Three-Prime RSA with Immunity Against Hardware Fault Attack (Abstract)

Z. Abid , University of Western Ontario, Canada
Yonghong Yang , University of Western Ontario, Canada
Wei Wang , University of Western Ontario, Canada
pp. 73-76

RNS Application for Digital Image Processing (Abstract)

M. N. S. Swamy , Concordia University, Montreal, Canada
M. O. Ahmad , Concordia University, Montreal, Canada
Wei Wang , The University of Western Ontario, London, Canada
pp. 77-80
Verification and Testing

Using Integer Equations to Check PSL Properties in RT Level Design (Abstract)

Bijan Alizadeh , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 83-86

Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models (Abstract)

S?bastien Regimbal , ?cole Polytechnique de Montr?al, Canada
Guy Bois , ?cole Polytechnique de Montr?al, Canada
Yvon Savaria , ?cole Polytechnique de Montr?al, Canada
pp. 87-92

Consistency Validation of High-Level Requirements (Abstract)

N. Gorse , Universit? de Montr?al
E. M. Aboulhamid , Universit? de Montr?al
Y. Savaria , Ecole Polytechnique de Montr?al
pp. 93-98

An Accurate Low Iteration Algorithm for Effective Capacitance Computation (Abstract)

Charles Chiang , Synopsys, Inc., Mountain View, CA
Yehea I. Ismail , Northwestern Univeristy, Evanston, IL
Shizhong Mei , Northwestern Univeristy, Evanston, IL
Jamil Kawa , Synopsys, Inc., Mountain View, CA
pp. 99-104

An Embedded Tester Core for System-on-Chip Architectures (Abstract)

R. Rashidzadeh , University of Windsor, Ontario, Canada
M. Ahmadi , University of Windsor, Ontario, Canada
W. C. Miller , University of Windsor, Ontario, Canada
pp. 105-108
Analog and Mixed Signal I

An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters (Abstract)

D. Morin , ?cole Polytechnique de Montr?al, Canada
M. Sawan , ?cole Polytechnique de Montr?al, Canada
F. Normandin , ?cole Polytechnique de Montr?al, Canada
M.-E. Grandmaison , ?cole Polytechnique de Montr?al, Canada
Y. Savaria , ?cole Polytechnique de Montr?al, Canada
H. Dang , ?cole Polytechnique de Montr?al, Canada
pp. 111-114

A CMOS High-Voltage DC-DC Up Converter Dedicated for Ultrasonic Applications (Abstract)

R. Chebli , ?cole Polytechnique de Montr?al
M. Sawan , ?cole Polytechnique de Montr?al
pp. 119-122

Possible Noise Failure Modes in Static and Dynamic Circuits (Abstract)

Yehea I. Ismail , Northwestern University, Evanston, IL
Masud H. Chowdhury , Northwestern University, Evanston, IL
pp. 123-126

Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
Donghoon Han , Georgia Institute of Technology, Atlanta
pp. 127-130

A Scalable Low-Voltage Extended Swing CMOS LC Quadrature VCO for RF Transceivers (Abstract)

S. M. Rezaul Hasan , University of Sharjah, United Arab Emirates
pp. 131-135

Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks (Abstract)

G. A. Jullien , University of Windsor, Canada
Y. Ibrahim , University of Windsor, Canada
W. C. Miller , University of Windsor, Canada
pp. 136-142
Video SoC Platform

Integrated Hardware-Software Platform for Image Processing Applications (Abstract)

Tamer S. Mohamed , University of Calgary, Canada
Wael Badawy , University of Calgary, Canada
pp. 145-148

An Efficient VLSI Implementation of MC Interpolation for MPEG-4 (Abstract)

Gao Wen , Chinese Academy of Science, Beijing, China
Ji Zhen Zhou , Dept. of Computer Science and Engineering Harbin Institute of Technology, China
Hu Ming Zeng , Dept. of Computer Science and Engineering Harbin Institute of Technology, China
Deng Lei , Dept. of Computer Science and Engineering Harbin Institute of Technology, China
pp. 149-152

A Novel Memory Architecture for Real-Time Mesh-based Video Motion Compensation (Abstract)

Mohammed Sayed , University of Calgary, Canada
Wael Badawy , University of Calgary, Canada
pp. 153-157

A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture (Abstract)

Jiang Li , Shanghai Jiao Tong University
Rong Meng-tian , Shanghai Jiao Tong University
Qiu Lin , Shanghai Jiao Tong University
Liu Ling-zhi , Shanghai Jiao Tong University
pp. 158-161

Real-time Audio/Video Decoders for Digital Multimedia Broadcasting (Abstract)

Victor H. S. Ha , Samsung Electronics Co., Ltd., Korea
Sung-Kyu Choi , Samsung Electronics Co., Ltd., Korea
Won-Kap Jang , Samsung Electronics Co., Ltd., Korea
Jong-Gu Jeon , Samsung Electronics Co., Ltd., Korea
Woo-Sung Shim , Samsung Electronics Co., Ltd., Korea
Geon-Hyoung Lee , Samsung Electronics Co., Ltd., Korea
pp. 162-167

Empirical Analysis of Operand Usage and Transport in Multimedia Applications (Abstract)

Linda M. Wills , Georgia Institute of Technology
D. Scott Wills , Georgia Institute of Technology
Hongkyu Kim , Georgia Institute of Technology
pp. 168-171

MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC (Abstract)

Yung-Chi Chang , National Taiwan University, Taipei
Chih-Wei Hsu , National Taiwan University, Taipei
Liang-Gee Chen , National Taiwan University, Taipei
pp. 172-175
Logic Synthesis

Observability-Based RTL Simulation using JAVA (Abstract)

Ashraf M. Salem , Mentor Graphics Egypt, Cairo, Egypt
Sherif G. Aly , General Dynamics, Cairo, Egypt
pp. 179-182

A Step towards Intelligent Translation from High-Level Design to RTL (Abstract)

?tienne Bergeron , Universit? de Montr?al
Jean Pierre David , Universit? de Montr?al
pp. 183-188

Towards Automating Hardware/Software Co-Design (Abstract)

M. W. El-Kharashi , Ain Shams University
A. Wahdan , Ain Shams University
M. H. El-Malaki , Mentor Graphics Egypt
A. Salem , Mentor Graphics Egypt
S. Hammad , Mentor Graphics Egypt
pp. 189-192

Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis (Abstract)

Ashwin K. Kumaraswamy , University of Edinburgh, UK
Ahmet T. Erdogan , University of Edinburgh, UK
Indrajit Atluri , University of Edinburgh, UK
pp. 193-197
Modeling and Simulation II

Taking Mixed-Signal Substrate Noise Coupling Simulation to the Behavioral level using SystemC (Abstract)

Jan Lundgren , Mid Sweden University, Sweden
Trond Ytterdal , Norwegian Univ. of Science and Tech., Trondheim, Norway
Mattias O'Nils , Mid Sweden University, Sweden
Kristian Vonbun , Norwegian Univ. of Science and Tech., Trondheim, Norway
pp. 201-205

Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems (Abstract)

Peter N. H. de With , LogicaCMG Nederland B.V., Eindhoven, The Netherlands; University of Technology Eindhoven, Eindhoven, The Netherlands
Dirk S. Farin , University of Technology Eindhoven, Eindhoven, The Netherlands
Peter Poplavko , University of Technology Eindhoven, Eindhoven, The Netherlands
Milan Pastrnak , LogicaCMG Nederland B.V., Eindhoven, The Netherlands; University of Technology Eindhoven, Eindhoven, The Netherlands
pp. 206-209

Design Strategies for ESD Protection in SOC (Abstract)

K. Iniewski , University of Alberta, Canada
A. Balasinski , Cypress Semiconductor, San Jose, CA
A. Shibkov , Sequoia Design Systems, Woodside, CA
V. Axelrad , Sequoia Design Systems, Woodside, CA
M. Syrzycki , Simon Fraser University, Canada
pp. 210-214

Bit Memory Instructions for a General CPU (Abstract)

Anders Edman , Linkopings universitet, Sweden
Dake Liu , Linkopings universitet, Sweden
Mikael Olausson , Linkopings universitet, Sweden
pp. 215-218

Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability (Abstract)

Keh-Jeng Chang , National Tsing Hua University, Hsin-Chu, Taiwan
pp. 219-222
Analog and Mixed Signal II

A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters (Abstract)

K. Ola Andersson , Link?ping University, Sweden
Mark Vesterbacka , Link?ping University, Sweden
pp. 225-228

Design of a Comparator in CMOS SOI (Abstract)

Mark Vesterbacka , Link?ping University, Sweden
Erik S?ll , Link?ping University, Sweden
pp. 229-232

A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18?m CMOS Technology (Abstract)

Iman Y. Taha , University of Windsor
M. Ahmadi , University of Windsor
W. C. Miller , University of Windsor
pp. 233-236

A Fully Automated Approach for Analog Circuit Reuse (Abstract)

Mohamed Dessouky , Ain Shams University, Cairo, Egypt
Mohamed Tawfik , Mentor Graphics Egypt, Cairo, Egypt
Sherif Hammouda , Mentor Graphics Egypt, Cairo, Egypt; University of Calgary, Alberta
Wael Badawy , University of Calgary, Alberta
pp. 237-240
OnChip Bus and Interconnect

Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing (Abstract)

Daoud Berkani , Signal & Communications Laboratory, Algiers, Algeria
Mountassar Maamoun , Blida University, Algeria
Boualem Laichi , USTHB, Algiers, Algeria
Abdelhalim Benbelkacem , LSIC Laboratory, Algiers, Algeria
pp. 243-246

SERDES Technology for Gigabit I/O Communications in Storage Area Networking (Abstract)

M. Syrzycki , Simon Fraser University, Canada
K. Iniewski , University of Alberta, Canada
M. Lapointe , Diablo Technologies, Canada
R. Badalone , Diablo Technologies, Canada
pp. 247-252

Evaluation of MP-SoC Interconnect Architectures: a Case Study (Abstract)

Michael Jones , University of British Columbia, Canada
Partha Pratim Pande , University of British Columbia, Canada
Cristian Grecu , University of British Columbia, Canada
Andr? Ivanov , University of British Columbia, Canada
Res Saleh , University of British Columbia, Canada
pp. 253-256

A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances (Abstract)

Henrik Ohlsson , Link?pings Universitet, Sweden
Jacob L?fvenberg , Link?pings Universitet, Sweden
Lars Wanhammar , Link?pings Universitet, Sweden
Kenny Johansson , Link?pings Universitet, Sweden
Tina Lindkvist , Link?pings Universitet, Sweden
pp. 257-262

Interconnect Synthesis for Systems on Chip (Abstract)

Neal K. Bambha , University of Maryland
Shuvra S. Bhattacharyya , University of Maryland
pp. 263-268

Network on Chip Simulations for Benchmarking (Abstract)

Sumant Sathe , Link?ping University, Sweden
Dake Liu , Link?ping University, Sweden
Daniel Wiklund , Link?ping University, Sweden
pp. 269-274

Non-Redundant Coding for Deep Sub-Micron Address Buses (Abstract)

Jacob L?fvenberg , Link?pings Universitet, Sweden
pp. 275-279
SoC Reconfigurable

RtrASSoc-Adaptable Superscalar Reconfigurable Programmable System on Chip-The Embedded Operating System - EOS (Abstract)

K. A. P. Costa , Universidade do Sagrado Cora??o, Brazil
J. L. Silva , Centro Universit?rio Eur?pides de Mar?ilia - UNIVEM, Brazil
pp. 283-286

ECOMIPS: An Economic MIPS CPU Design on FPGA (Abstract)

Xizhi Li , The CKC honored School of Zhejiang University, P.R. China
Tiecai Li , Harbin Institute of Technology
pp. 291-294

A Field Programmable Bit-Serial Digital Signal Processor (Abstract)

L. E. Turner , University of Calgary
S. A. Rahim , University of Calgary
pp. 295-298

A Customizable Embedded SoC Platform Architecture (Abstract)

Yvon Savaria , Department of EE Ecole Polytechnique, Montreal, QC, Canada
Pascal Nsame , Department of EE Ecole Polytechnique, Montreal, QC, Canada
pp. 299-304
SoC for Network and Communication Applications

SOC Design of an IF Subsampling Terminal for a Gigabit Wireless LAN with Asymmetric Equalization (Abstract)

Grant McGibney , University of Calgary
Jim Kulyk , University of Calgary
Holly Pekau , University of Calgary
James W. Haslett , University of Calgary
Joshua K. Nakaska , University of Calgary
pp. 307-313

Reconfigurable 2.5 GHz Phase-Locked Loop for System on Chip Applications (Abstract)

S. Magierowski , University of Calgary, Canada
K. Iniewski , University of Alberta, Canada
M. Syrzycki , Simon Fraser University, Canada
pp. 314-317

SoC Features for a Multi-Processor WCDMA Base-station Modem (Abstract)

Allan Dyck , Cogent ChipWare Inc. and Simon Fraser University
Richard Hobson , Cogent ChipWare Inc. and Simon Fraser University
Keith Cheung , Cogent ChipWare Inc. and Simon Fraser University
pp. 318-321

Author Index (PDF)

pp. 323-324
96 ms
(Ver 3.3 (11022016))