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System-on-Chip for Real-Time Applications, International Workshop on (2003)
Calgary, Alberta, Canada
June 30, 2003 to July 2, 2003
ISBN: 0-7695-1944-X
TABLE OF CONTENTS
SoC Design Methodologies 1

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Template Generation and Selection Algorithms (Abstract)

Hajo Broersma , University of Twente, Faculty of EEMCS
Paul M. Heysters , University of Twente, Faculty of EEMCS
Yuanqing Guo , University of Twente, Faculty of EEMCS
Gerard J.M. Smit , University of Twente, Faculty of EEMCS
pp. 2

Optimized Datapath Design by Evolutionary Computation (Abstract)

A. C. P. Pedroza , Electrical Engineering Dept. - UFRJ
S. G. Ara? , Electrical Engineering Dept. - UFRJ
A. C. Mesquita , Electrical Engineering Dept. - UFRJ
pp. 6

A performance evaluation method for optimizing embedded applications (Abstract)

Matthias Gr?newald , University of Paderborn, Germany
Ulrich Ruckert , University of Paderborn, Germany
J?rg-Christian Niemann , University of Paderborn, Germany
pp. 10
SoC Physical Design - Invited

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Detailed Placement with Net Length Constraints (Abstract)

Naresh Sehgal , Intel Corporation
Bill Halpin , Syracuse University
C.Y. Roger Chen , Syracuse University
pp. 22

STEINER TREE CONSTRUCTION BASED ON CONGESTION FOR THE GLOBAL ROUTING PROBLEM (Abstract)

Laleh Behjat , University of Calgary, Calgary, Alberta, Canada
Anthony Vannelli , University of Calgary, Calgary, Alberta, Canada
pp. 28

InterconnectionModelling Using Distributed RLC Models (Abstract)

Anthony Vannelli , University of Waterloo
Dorothy Kucar , University of Waterloo
pp. 32
Low Power SoCs

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A Survey of Dynamic Power Optimization Techniques (Abstract)

XiaoJun Wang , Dublin City University
Li-Chuan Weng , Dublin City University
Bin Liu , TsingHua University
pp. 48

The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks (Abstract)

A. Carreira , University of Calgary
L.E. Turner , University of Calgary
T.W. Fox , Intelligent Engines
pp. 53
Arithmetic Techniques

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IP Watermarking Techniques: Survey and Comparison (Abstract)

Sofiene Tahar , Concordia University
Amr T. Abdel-Hamid , Concordia University
El Mostapha Aboulhamid , Universite de Montreal
pp. 60

The Application of 2D Algebraic Integer Encoding to a DCT IP Core (Abstract)

G. A. Jullien , RCIM Research Centre, University of Windsor
M. Ahma , RCIM Research Centre, University of Windsor
Minyi Fu , RCIM Research Centre, University of Windsor
V. S. Dimitrov , RCIM Research Centre, University of Windsor
W. C. Miller , RCIM Research Centre, University of Windsor
pp. 66

Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic (Abstract)

Boris D. Andreev , University of Rochester
Edward L. Titlebaum , University of Rochester
Eby G. Friedman , University of Rochester
pp. 70

Digital Realization of Analogue Computing Elements Using Bit Streams (Abstract)

Sing Kiong Nguang , University of Auckland, New Zealand
George Coghill , University of Auckland, New Zealand
Nitish Patel , University of Auckland, New Zealand
pp. 76
Analog and Mixed Signals 1

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A Design of CMOS Broadband Amplifier With High-Q Active Inductor (Abstract)

Chen-Yi Lee , National Chiao Tung University
Jhy-Neng Yang , National Chiao Tung University
Yi-Chang Cheng , Minghsin University of Science Technology
pp. 86

A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation (Abstract)

Yu-Lung Lo , Tamkang University, Taipei Hsien, Taiwan, R.O.C.
Wen-Fang Yu , Tamkang University, Taipei Hsien, Taiwan, R.O.C.
Kuo-Hsing Cheng , Tamkang University, Taipei Hsien, Taiwan, R.O.C.
Shu-Yin Hung , Tamkang University, Taipei Hsien, Taiwan, R.O.C.
pp. 90

A 5.8-GHz High Efficient, Low Power, Low Phase Noise CMOS VCO for IEEE 802.11a (Abstract)

Wei-Liang Chen , Yuan-Ze University
Sau-Mou Wu , Yuan-Ze University
Ron-Yi Liu , Yuan-Ze University
pp. 94

A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18?m CMOS Technology (Abstract)

Stephen Machan , Florida Communications Research Labs, Motorola Labs
pp. 98
Reconfigurable Hardware

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Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip (Abstract)

Neil Bergmann , School of ITEE, University of Queensland
Peter Waldeck , School of ITEE, University of Queensland
pp. 102

Hardware Partitioning Software for Dynamically Reconfigurable SoC Design (Abstract)

C. Tanougast , Laboratoire d?Instrumentation Electronique de Nancy, Vandoeuvre L?s Nancy, France
P. Brunet , Laboratoire d?Instrumentation Electronique de Nancy, Vandoeuvre L?s Nancy, France
S. Weber , Laboratoire d?Instrumentation Electronique de Nancy, Vandoeuvre L?s Nancy, France
Y. Berviller , Laboratoire d?Instrumentation Electronique de Nancy, Vandoeuvre L?s Nancy, France
pp. 106

Reconfigurable Digital Instrumentation Based on FPGA (Abstract)

Antonio Di Stefano , University of Palermo I-90128, Italy
Costantino Giaconia , University of Palermo I-90128, Italy
Giuseppe Capponi , University of Palermo I-90128, Italy
pp. 120

Introducing an FPGA based - genetic algorithms in the applications of blind signals separation (Abstract)

H. Emam , NCRRT, Cairo, Egypt
A. M. Wahdan , Ain Shams Univ., Cairo, Egypt
H. Fekry , Ain Shams Univ., Cairo, Egypt
M. A. Ashour , NCRRT, Cairo, Egypt
pp. 123
Digital Circuits

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A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems (Abstract)

Shih-Chang Hsia , University of Science and Technology, Kaohsiung 824, Taiwan, R.O.C.
pp. 130

Area Efficient Implementation of Noise Generation System (Abstract)

Dae-Ik Kim , Yosu Nat?l Univ., Yeosu, 550-749, KOREA
Ho-Yong Chung , Yosu Nat?l Univ., Yeosu, 550-749, KOREA
Suk-Young Kim , Kunsan Nat?l Univ., Kunsan, 573-701, KOREA
Myung-Whan An , Yosu Nat?l Univ., Yeosu, 550-749, KOREA
pp. 134

High-performance crossbar design for system-on-chip (Abstract)

Panduka Wijetunga , University of Southern California, Los Angeles, CA 90089
pp. 138

Interfacing in Microprocessor-based Systems with a Fast Physical Addressing. (Abstract)

Abdelhalim Benbelkacem , LSIC Laboratory, (ENS)
Mountassar Maamoun , Blida University
A. Guessoum , Blida University
D. Berkani , Laboratory, (ENP)
pp. 144
SoC Applications 1

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FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS (Abstract)

Andrew Y. Lin , Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida
Jos? C. Pr?ncipe , Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida
Karl S. G ugel , Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida
pp. 157

Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem (Abstract)

L. Serafini , Engineering, University of Pisa, Italy,
S. Saponara , Engineering, University of Pisa,
L. Fanucci , Council, Pisa, Italy,
pp. 161

VLSI IMPLEMENTATION OF VERY LOW-POWER MOTION ESTIMATOR FOR SCALEABLE CODING SYSTEMS (Abstract)

Shih-Chang Hsia , Department of Computer and Communication Engineering, National Kaohsiung First University
pp. 167
Modeling Issues in SoCs

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A CMOS inverter TIA modeling with VHDL-AMS (Abstract)

Patricia DESGREYS , Ecole Nationale Sup?rieure des T?l?communications
Jean-Jacques CHARLOT , Ecole Nationale Sup?rieure des T?l?communications
Mohamed KARRAY , Ecole Nationale Sup?rieure des T?l?communications
pp. 172

High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim (Abstract)

Armando Armaroli , DEIT, University of Pisa
Mario Diaz Nava , STMicroelectronics rue Jules Horowith, 12
Marcello Coppola , STMicroelectronics
Luca Luca Fanucci , IEIIT-CNR
pp. 175

Java Based Co-Verification of Expedited Mobile Device (Abstract)

Sherif G. Aly , General Dynamics Cairo, Egypt
Ashraf M. Salem , Mentor Graphics Egypt Cairo, Egypt
pp. 181
Embedded Processors

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Evaluating Template-Based Instruction Compression on Transport Triggered Architectures (Abstract)

Tommi Rantanen , Tampere University of Technology
Jarmo Takala , Tampere University of Technology
Henk Corporaal , Eindhoven University of Technology
Jari Heikkinen , Tampere University of Technology
Andrea Cilio , Tampere University of Technology
pp. 192

RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip (Abstract)

R.M. Costa , Programa de P?s-Gradua??o em Ci?ncia da Computa??
J. L. Silva , Programa de P?s-Gradua??o em Ci?ncia da Computa??
G. H. R. Jorge , Universidade do Sagrado Cora??o de Jesus
pp. 196

Pullpipelining: A technique for systolic pipelined circuits (Abstract)

Oswaldo Cadenas , University of Reading, School of Systems Engineering,
Graham Megson , University of Reading, School of Systems Engineering,
pp. 205
SoC Design Methodologies 2

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A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design (Abstract)

Sofi?ne Tahar , Concordia University, Montreal, Quebec, Canada
Ali Habibi , Concordia University, Montreal, Quebec, Canada
pp. 212

Scaleable Shadow Stack for a Configurable DSP Concept (Abstract)

Jari Nurmi , Tampere University of Technology
Christian Panis , Carinthian Tech Institute
Raimund Leitner , Infineon Technologies
pp. 222

Automating Functional Coverage Analysis Based on an Executable Specification (Abstract)

Yvon Savaria , ?cole Polytechnique de Montr?al
S?bastien Regimbal , ?cole Polytechnique de Montr?al
Andr? Baron , PMC-Sierra, Montr?al
El Mostapha Aboulhamid , Universit? de Montr?al
Jean-Fran?ois Lemire , ?cole Polytechnique de Montr?al
Guy Bois , ?cole Polytechnique de Montr?al
pp. 228
Sensors

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A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and Actuators (Abstract)

F. Campi , ARCES, University of Bologna, Italy
G. Medoro , Silicon Biosystems, Italy
M. Tartagni , ARCES, University of Bologna, Italy
N. Manaresi , Silicon Biosystems, Italy
S. Ronconi , ARCES, University of Bologna, Italy
pp. 236

Porosity Sensor by Using Quartz Crystals and Two Excitation Signals (Abstract)

Vojko Matko , University of Maribor, Faculty of Electrical Engineering and Computer Science
pp. 242

Pipelined Sampled-Delay Focusing CMOS Implementation for Ultrasonic Digital Beamforming (Abstract)

A. Kassem , ?cole Polytechnique de Montr?al
A. Khouas , ?cole Polytechnique de Montr?al
M. Sawan , ?cole Polytechnique de Montr?al
M. Boukadoum , Department of computer Sciences, Universit? du Qu?bec ? Montr?al
J. Wang , ?cole Polytechnique de Montr?al
pp. 247

Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors (Abstract)

Jose Vicente Calvano , Brazilian Navy Research Institute
Marcelo Soares Lubaszewski , Federal University of Rio Grande do Sul
pp. 251
Analog and Mixed Signals 2

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A 0.28?m CMOS Bluetooth Frequency Synthesizer for Integration with a Bluetooth SOC Reference Platform (Abstract)

Bogdan A. Georgescu , University of Calgary, Department of Electrical and Computer Engineering
Joshua K. Nakaska , University of Calgary, Department of Electrical and Computer Engineering
pp. 258

A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology (Abstract)

Alper Cabuk , Nanyang Technological University, eljia@ntu.edu.sg
Lin Jia , Nanyang Technological University, eljia@ntu.edu.sg
Kiat Seng Yeo , Nanyang Technological University, eljia@ntu.edu.sg
Jian-Guo Ma , Nanyang Technological University, eljia@ntu.edu.sg
pp. 264

Novel Design Methodology for Short-Channel MOSFET Analog Circuits (Abstract)

F. Maloberti , The University of Texas at Dallas, USA
R. L. Oliveira Pinto , Texas A & M University, USA
pp. 270

120nm CMOS Operational Amplifier with Pseudo-Cascodes and Positive Feedback (Abstract)

H. Zimmermann , Institute for Electrical Measurements and Circuit Design
pp. 277

The Implementation of 100MHz Data Acquisition Based on FPGA (Abstract)

Tao Lin , Southwest China Research Institute of Electronic, Equipment, P. O. Box 429
Zhou Zhengou , College of Electronic Engineering, University of Electronic Science & Technology of China,
pp. 287
Interconnect

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Free-Space Optical Interconnect for High-Performance MCM Systems (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Chung-Seok (Andy) Seo , Georgia Institute of Technology
pp. 294

Design Considerations for Optically Connected Systems on Chip (Abstract)

Shuvra S. Bhattacharyya , University of Maryland, College Park USA
Neal K. Bambha , University of Maryland, College Park USA
Gary Euliss , Fairfax, VA USA
pp. 299

High-Throughput Switch-Based Interconnect for Future SoCs (Abstract)

Andr? Ivanov , University of British Columbia
Partha Pratim Pande , University of British Columbia
Cristian Grecu , University of British Columbia
pp. 304

THE EFFICIENT BUS ARBITRATION SCHEME IN SOC ENVIRONMENT (Abstract)

Hi Seok Kim , Chongju University, Chongju, KOREA
Chi Ho Lin , Semyung University, Checheon, KOREA
Chang Hee Pyoun , Hanyang University, Seoul, KOREA, Department of Electronics Engineering
Jong Wha Chong , Hanyang University, Seoul, KOREA, Department of Electronics Engineering
pp. 311

The Glue in a Confident SoC Flow (Abstract)

John Ferguson, Ph.D. , Mentor Graphics Corp. Wilsonville, Oregon
pp. 316

Analysis of Coupling Noise in Dynamic Circuit (Abstract)

Masud H. Chowdhury , Northwestern University, Evanston, IL 60208, USA
Yehea I. Ismail , Northwestern University, Evanston, IL 60208, USA
pp. 320
Memory Techniques for SoCs

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A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications (Abstract)

Mohammed Sayed , Department of Electrical and Computer Engineering, University of Calgary
Wael Badawy , Department of Electrical and Computer Engineering, University of Calgary
pp. 328

Efficient Distributed Arithmetic Based DWT Architecture for Multimedia Applications (Abstract)

Wael Badawy , University of Calgary
Mehboob Alam , University of Calgary
Graham J ullien , University of Calgary
Choudhury A. Rahman , University of Calgary
pp. 333

AN EFFICIENT EQUALIZER ARCHITECTURE USING TAP ALLOCATION MEMORY FOR HDTV CHANNEL (Abstract)

Min Ho Kim , Samsung Electronics System LSI Division
Jong Wha Chong , Hanyang University, Seoul, KOREA, Department of Electronics Engineering
Jung Min Choi , Hanyang University, Seoul, KOREA, Department of Electronics Engineering
Jae Hong Park , Hanyang University, Seoul, KOREA, Department of Electronics Engineering
pp. 343
SoC Medical Applications

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A SoC Bio-analysis Platform for Real-time Biological Cell Analysis-on-a-Chip (Abstract)

K.V.I.S Kaler , University of Calgary
G.A. Jullien , University of Calgary
J.R. Keilman , University of Calgary
pp. 362
SoC Testing

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An Efficient Mechanism for Debugging RTL Description (Abstract)

Chia-Hung Lin , Department of Electrical Engineering, Tamkang University
Yi-Yuan Chang , Department of Electrical Engineering, Tamkang University
Jiann-Chyi Rau , Department of Electrical Engineering, Tamkang University
pp. 370

An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits (Abstract)

Kuo-Chun Kuo , Department of Electrical Engineering, Tamkang University
Jiann-Chyi Rau , Department of Electrical Engineering, Tamkang University
pp. 374

Symbolic Simulation as a Simplifying Strategy for SoC Verification (Abstract)

Dominique BORRIONE , TIMA Laboratory, Grenoble, FRANCE
Emil DUMITRESCU , TIMA Laboratory, Grenoble, FRANCE
pp. 378
SoC Applications 2

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A QoS Internet Protocol Scheduler on the IXP1200 Network Platform (Abstract)

L. Fanucci , IEIIT-CNR
F. De Bernardinis , DEIT, University of Pisa
P. Terreni , DEIT, University of Pisa
T. Ramacciotti , DEIT, University of Pisa
pp. 394

A POSITION CONTROL SYSTEM DESIGN (Abstract)

Robert Gulde , Georgia State University
Michael Weeks , Georgia State University
pp. 400
Author Index

Author Index (PDF)

pp. 407
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