System-on-Chip for Real-Time Applications, International Workshop on (2003)
Calgary, Alberta, Canada
June 30, 2003 to July 2, 2003
Tao Lin , Southwest China Research Institute of Electronic, Equipment, P. O. Box 429
Zhou Zhengou , College of Electronic Engineering, University of Electronic Science & Technology of China,
A high-speed data acquisition based on FPGA and implemented in VHDL is presented in this paper. According to the requirement of a new radar system, several new technologies are adopted in the design and implementation such as Time Compression Storage and Memory Rewriting. As a result, the system performs well with low dissipation of power, simple circuit layout and high efficient utilization of memory. The acquisition system comprises four parts: ADC circuit, Data Package and Interface, Sampling Data Memory and data Flag Memory. To implement large circuit, FPGA is adopted in this data acquisition system with reconfigurable ability and constant delay feature .
Compression Sampling, field programmable gate array (FPGA), VHDL, flag, memory, Top-Down
T. Lin and Z. Zhengou, "The Implementation of 100MHz Data Acquisition Based on FPGA," System-on-Chip for Real-Time Applications, International Workshop on(IWSOC), Calgary, Alberta, Canada, 2003, pp. 287.