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Extended Abstracts of the Third International Workshop on Junction Technology. IWJT (2002)
Tokyo, Japan
Dec. 2, 2002 to Dec. 3, 2002
ISBN: 4-89114-028-3
TABLE OF CONTENTS

[Front matter] (PDF)

pp. 0_1

Detailed modeling of source/drain parasitics and their impact on MOSFETs scaling (PDF)

Seong-Dong Kim , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
J.C.S. Woo , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 1-4

SOI formation by light ion implantation and annealing in oxygen including atmosphere (PDF)

A. Ogura , Silicon Syst. Res. Lab., NEC Corp., Sagamihara, Japan
pp. 5-8

Doping accuracy requirements of USJ processes for advanced sub-100 nm CMOS devices (PDF)

A. Murrell , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
H. Graoui , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
J. Spear , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
H. Ito , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
Y. Matsunaga , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
A. Al-Bayati , Parametric & Conductive Implant Div., Appl. Mater. Inc., Santa Clara, CA, USA
pp. 9-13

The angle control within a wafer in high-energy implanter of batch type (PDF)

Y. Kawasaki , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
T. Yamashita , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
M. Kitazawa , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
T. Kuroi , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Y. Ohno , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
M. Yoneda , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
pp. 15-17

The drain current asymmetry of 130 nm MOSFETs due to extension implant shadowing originated by mechanical angle error in high current implanter (PDF)

K. Yoneda , ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co., LTD, Kyoto, Japan
M. Niwayama , ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co., LTD, Kyoto, Japan
pp. 19-22

Flash lamp annealing technology for ultra-shallow junction formation (PDF)

T. Ito , Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
K. Suguro , Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
pp. 23-26

Influence of pulse duration on KrF excimer laser annealing process for ultra shallow junction formation (PDF)

K. Kagawa , Res. Div., Komatsu Ltd., Kanagawa, Japan
Y. Niwatsukino , Res. Div., Komatsu Ltd., Kanagawa, Japan
A. Matsuno , Res. Div., Komatsu Ltd., Kanagawa, Japan
pp. 31-34

Formation of low-resistive ultra-shallow n+/p junction by heat-assisted excimer laser annealing (PDF)

K. Kurobe , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Y. Ishikawa , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
pp. 35-36

Helicon wave plasma doping system (PDF)

Y. Sasaki , Ultimate Junction Technol. Inc., Moriguchi, Japan
B. Mizuno , Ultimate Junction Technol. Inc., Moriguchi, Japan
pp. 37-38

Gas phase doping at room temperature (PDF)

Y. Sasaki , Ultimate Junction Technol. Inc.,, Moriguchi, Japan
B. Mizuno , Ultimate Junction Technol. Inc.,, Moriguchi, Japan
pp. 39-40

Gate insulating layer impact on the extension profile of the sub-50 nm p-MOSFET (PDF)

H. Fukutome , Fujitsu Labs. Ltd., Tokyo, Japan
H. Arimoto , Fujitsu Labs. Ltd., Tokyo, Japan
S. Watanabe , Fujitsu Labs. Ltd., Tokyo, Japan
pp. 43-46

Evaluation of BN-delta-doped multilayer reference materials for shallow depth profiling in SIMS (PDF)

S. Yoshikawa , Matsushita Technores. Inc., Moriguchi, Japan
F. Toujou , Matsushita Technores. Inc., Moriguchi, Japan
pp. 47-48

Photoluminescence and ab initio study of {311} defect nucleation in Si (PDF)

H. Tsuji , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
R. Kim , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
T. Hirose , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
M. Furuhashi , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
M. Tachi , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
K. Taniguchi , Dept. of Electron. & Inf. Sys., Osaka Univ., Suita Osaka, Japan
pp. 49-50

Source/drain elevation process using implantation enhanced selective etching (PDF)

M.Q. Huda , Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
K. Sakamoto , Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
H. Tanoue , Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
pp. 51-54

Elevated source/drain engineering with smooth surface morphology for ultrathin-SOI CMOS (PDF)

K. Sugihara , Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan
T. Nakahata , Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan
pp. 55-58

Ultra shallow sidewall GaAs tunnel junctions implemented with molecular layer epitaxy (PDF)

T. Ohno , Dept. of Mater. Sci., Tohoku Univ., Sendai, Japan
Y. Oyama , Dept. of Mater. Sci., Tohoku Univ., Sendai, Japan
K. Tezuka , Dept. of Mater. Sci., Tohoku Univ., Sendai, Japan
K. Suto , Dept. of Mater. Sci., Tohoku Univ., Sendai, Japan
pp. 59-62

SOI NMOSFETs with SiGe elevated S/D and Ni silicide (PDF)

Hoon Choi , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
Hyuckjae Oh , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
JeoungChill Shim , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
T. Sakaguchi , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
H. Kurino , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
M. Koyanagi , Dept. of Machine Intelligence & Syst. Eng., Tohoku Univ., Sendai, Japan
pp. 63-64

Suppression of migration during low pressure annealing for selective epitaxial growth on ultra-thin SOI (PDF)

I. Mizushima , Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
T. Sato , Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
K. Miyano , Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
Y. Tsunashima , Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
pp. 65-66

Silicide technology for USJ in next technology node (PDF)

K. Suguro , Semicond. Co., Toshiba Corp., Yokohama, Japan
T. Iinuma , Semicond. Co., Toshiba Corp., Yokohama, Japan
M. Izuha , Semicond. Co., Toshiba Corp., Yokohama, Japan
K. Ohuchi , Semicond. Co., Toshiba Corp., Yokohama, Japan
A. Hokazono , Semicond. Co., Toshiba Corp., Yokohama, Japan
K. Miyano , Semicond. Co., Toshiba Corp., Yokohama, Japan
I. Mizushima , Semicond. Co., Toshiba Corp., Yokohama, Japan
pp. 67-70

Improvement in morphology of nickel silicide film with carbon (PDF)

O. Nakatsuka , Center for Integrated Res. in Sci. & Eng., Nagoya Univ., Japan
pp. 71-72

Influence of a small amount of oxygen during rapid thermal processing on cobalt salicide at 65 nm gate length (PDF)

Y. Kanda , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
M. Ogura , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
K. Honda , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
S. Tsutsumi , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
K. Maekawa , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
K. Kobayashi , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
M. Yoneda , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
pp. 73-74

TCAD simulation in development and fabrication of deep-sub-/spl mu/m devices (PDF)

A. Erlebach , Parametric & Conductive Implant Div., Appl. Mater., Santa Clara, CA, USA
C. Zechner , Parametric & Conductive Implant Div., Appl. Mater., Santa Clara, CA, USA
pp. 81-84

Low temperature activation of ion implanted dopants: a review (PDF)

J.O. Borland , Varian Semicond. Equip. Associates, Newburyport, MA, USA
pp. 85-88

As and Sb diffusion profiles in thin silicon-on-insulator wafers (PDF)

Y. Shibata , Dept. of Electr. & Comput. Eng., Nagoya Inst. of Technol., Japan
M. Ichimura , Dept. of Electr. & Comput. Eng., Nagoya Inst. of Technol., Japan
E. Arai , Dept. of Electr. & Comput. Eng., Nagoya Inst. of Technol., Japan
pp. 89-90

Bulk CMOS technology for SOC (PDF)

C.H. Diaz , Sci.-Based Ind. Park, Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
pp. 91-95

Nanocleaving: an enabling technology for ultra-thin SOI (PDF)

M.I. Current , Silicon Genesis Corp., San Jose, USA
pp. 97-101

S/D extension formation utilizing offset spacer for 65 nm node high performance CMOS (PDF)

K. Adachi , SoC Res. & Dev. Center, Toshiba Corp. Semicon. Co., Kanagawa, Japan
K. Ohuchi , SoC Res. & Dev. Center, Toshiba Corp. Semicon. Co., Kanagawa, Japan
Y. Toyoshima , SoC Res. & Dev. Center, Toshiba Corp. Semicon. Co., Kanagawa, Japan
pp. 103-104

SOI technology for future SoC (PDF)

Y. Inoue , ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
pp. 107-108
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