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International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06) (2006)
Kohala Coast, Hawaii
Jan. 23, 2006 to Jan. 25, 2006
ISSN: 1527-1366
ISBN: 0-7695-2689-6
TABLE OF CONTENTS
Introduction
Supercomputers

A Holistic Approach to System Reliability in Blue Gene (Abstract)

M. Blumrich , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
D. Chen , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
G. L. -T. Chiu , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
T. Cipolla , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
P. Coteus , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
P. Crumley , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
A. Gara , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
M.E. Giampapa , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
S. Hall , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
R.A. Haring , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
P. Heidelberger , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
D. Hoenicke , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
G.V. Kopcsay , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
T.A. Liebsch , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
L. Mok , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
M. Ohmacht , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
V. Salapura , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
R. Swetz , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
T. Takken , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
P. Vranas , IBM T.J. Watson Research Center, USA; IBM Rochester, USA
pp. 3-12
Processors

Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips (Abstract)

Peter M. Kogge , Univ. of Notre Dame, USA
Jay B. Brockman , Univ. of Notre Dame, USA
pp. 13-20

Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors (Abstract)

Toshinori Sato , Kyushu University, Japan
Akihiro Chiyonobu , Kyushu Institute of Technology, Japan
Kazuki Joe , Nara Women's University, Japan
pp. 21-28

The Speculative Prefetcher and Evaluator Processor for Pipelined Memory Hierarchies (Abstract)

Gianfranco Bilardi , Universita di Padova, Italy; T.J. Watson Research Center, IBM, USA
Kattamuri Ekanadham , T.J. Watson Research Center, IBM, USA
Pratap Pattnaik , T.J. Watson Research Center, IBM, USA
pp. 29-43
Networks

A Partial Irregular-Network Routing on Faulty k-ary n-cubes (Abstract)

Michihiro Koibuchi , National Institute of Informatics, Japan
Tsutomu Yoshinaga , University of Electro-Communications, Japan
Yasuhiko Nishimura , University of Electro-Communications, Japan
pp. 57-64

Predictive Switching in 2-D Torus Routers (Abstract)

Tsutomu Yoshinaga , University of Electro-Communications, Japan
Shojiro Kamakura , University of Electro-Communications, Japan
Michihiro Koibuchi , National Institute of Informatics, Japan
pp. 65-72

Hardware Support for MPI in DIMMnet-2 Network Interface (Abstract)

Noboru Tanabe , Toshiba
Akira Kitamura , Keio University, Japan
Tomotaka Miyashiro , Keio University, Japan
Yasuo Miyabe , Keio University, Japan
Takeshi Araki , Tokyo University of Agriculture and Technology, Japan
Zhengzhe Luo , Tokyo University of Agriculture and Technology, Japan
Hironori Nakajo , Tokyo University of Agriculture and Technology, Japan
Hideharu Amano , Keio University, Japan
pp. 73-82
OS & Compilers

Compilation for Delay Impact Minimization in VLIW Embedded Systems (Abstract)

Jose L. Ayala , Universidad Politecnica de Madrid, Spain
David Atienza , Universidad Complutense de Madrid, Spain
Praveen Raghavan , IMEC, Belgium
Marisa Lopez-Vallejo , Universidad Politecnica de Madrid, Spain
Francky Catthoor , IMEC, Belgium
pp. 83-90

Real-Time Operating System Kernel for Multithreaded Processor (Abstract)

Kiyofumi Tanaka , Japan Advanced Institute of Science and Technology, Japan
pp. 91-100
Author Index

Author Index (PDF)

pp. 101
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