The Community for Technology Leaders
2010 International Workshop on Innovative Architecture for Future Generation High Performance (2005)
Oahu, Hawaii
Jan. 17, 2005 to Jan. 19, 2005
ISSN: 1527-1366
ISBN: 0-7695-2483-4

Committees (PDF)

pp. viii
Chapter 1

Superscalar Processor with Multi-Bank Register File (Abstract)

Tetsuya Sueyoshi , Hiroshima University
Kenichi Aoyama , Hiroshima University
Tetsuo Hironaka , Hiroshima City University
Hans Juergen Mattausch , Hiroshima University
Moto Maeda , Hiroshima City University
Tadashi Saito , Hiroshima City University
Tetsushi Koide , Hiroshima University
Kazuya Tanigawa , Hiroshima City University
pp. 3-12
Chapter 2

Steering and Forwarding Techniques for Reducing Memory Communication on a Clustered Microarchitecture (Abstract)

Hidetsugu Irie , Japan Science and Technology Agency and University of Tokyo
Naoya Hatta , University of Tokyo
Takashi Toyoshima , University of Tokyo
Suichi Sakai , University of Tokyo
Naoya Hattori , Hitachi, Ltd.
Masanori Takada , Hitachi, Ltd.
pp. 13-18
Chapter 3

The Bimode++ Branch Predictor (Abstract)

Hiroki Honda , University of Electro-Communications
Toshitsugu Yuba , University of Electro-Communications
Takahiro Katagiri , University of Electro-Communications
Kenji Kise , University of Electro-Communications and Japan Science and Technology Agency
pp. 19-26
Chapter 4

On the Use of Bit Filters in Shared Nothing Partitioned Systems (Abstract)

Josep-L. Larriba-Pey , Universitat Politecnica de Catalunya
Hebert Pereyra , IBM Toronto Lab.
Victor Muntes-Mulero , Universitat Politecnica de Catalunya
Calisto Zuzarte , IBM Toronto Lab.
Josep Aguilar-Saborit , Universitat Politecnica de Catalunya
pp. 29-37
Chapter 5

Incorporating a Secure Coprocessor in the Database-as-a-Service Model (Abstract)

Gene Tsudik , University of California at Irvine
Einar Mykletun , University of California at Irvine
pp. 38-44
Chapter 6

Understanding and Comparing the Performance of Optimized JVMs (Abstract)

Alex Veidenbaum , University of California at Irvine
Dan Nicolaescu , University of California at Irvine
pp. 45-52
Chapter 7
Chapter 8

Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs (Abstract)

David Atienza , Universidad Complutense de Madrid
C. A. López-Barrio , Universidad Politécnica de Madrid
Marisa López-Vallejo , Universidad Politécnica de Madrid
R. Hermida , Universidad Complutense de Madrid
J. M. Mendías , Universidad Complutense de Madrid
José L. Ayala , Universidad Politécnica de Madrid
pp. 65-71
Chapter 9
Chapter 10

A Multi-Thread Processor Architecture Based on the Continuation Model (Abstract)

Masaaki Izumi , Kyushu University
Satoshi Amamiya , Kyushu University
Makoto Amamiya , Kyushu University
Takanori Matsuzaki , Kyushu University
pp. 83-90
Chapter 11

PRESTOR-1: A Processor Extending Multithreaded Architecture (Abstract)

Kiyofumi Tanaka , Japan Advanced Institute of Science and Technology
pp. 91-98
Chapter 12

Continuum Computer Architecture for Nano-Scale and Ultra-High Clock Rate Technologies (Abstract)

Thomas Sterling , California Institute of Technology
Maciej Brodowicz , Louisiana State University
pp. 101-109
Chapter 13

Performance Evaluation of Dynamic Network Reconfiguration Using Detour-UD Routing (Abstract)

Yasuhiko Nishimura , University of Electro-Communications
Tsutomu Yoshinaga , University of Electro-Communications
pp. 110-118
Chapter 14

Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface (Abstract)

Tomotaka Miyashiro , Keio University
Yoshihiro Hamada , Tokyo University of Agriculture and Technology
Hideharu Amano , Keio University
Yasuo Miyabe , Keio University
Hironori Nakajo , Tokyo University of Agriculture and Technology
Tohru Izawa , Keio University
Akira Kitamura , Keio University
Noboru Tanabe , Toshiba Corporation
pp. 119-127
Chapter 15

SIMD Optimization in COINS Compiler Infrastructure (Abstract)

Nobuhisa Fujinami , Sony Computer Entertainment Inc.
Ikuo Nakata , Hosei University
Tan Watanabe , University of Electro-Communications
Mitsugu Suzuki , University of Electro-Communications
Takeaki Fukuoka , Kanrikogaku Kenkyusho, Ltd.
pp. 131-140
Chapter 16

Performance Comparison of Vector-Calculations between Itanium2 and other Processors (Abstract)

Hiroyuki Sato , University of Tokyo
Yoshitaka Watanabe , Kyushu University
Takeshi Nanri , Kyushu University
pp. 141-146
Author Index

Author Index (PDF)

pp. 147
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