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2010 International Workshop on Innovative Architecture for Future Generation High Performance (2004)
Maui, Hawaii
Jan. 12, 2004 to Jan. 14, 2004
ISSN: 1527-1366
ISBN: 0-7695-2205-X
TABLE OF CONTENTS

Preface (PDF)

pp. vii

Program Committee (PDF)

pp. viii-viiii
High Performance, Low-Power Architectures

Direct Instruction Wakeup for Out-of-Order Processors (Abstract)

Mateo Valero , U.P.C., Barcelona Spain
Adrian Cristal , U.P.C., Barcelona Spain
Alexander V. Veidenbaum , University of California Irvine, USA
Marco A. Ram?rez , U.P.C., Barcelona Spain; National Polytechnic Institute, M?xico
Luis Villa , Mexican Petroleum Institute, Mexico
pp. 2-9

A Super Instruction-Flow Architecture for High Performance and Low Power Processors (Abstract)

Toshitsugu Yuba , The University of Electro-Communications
Hiroki Honda , The University of Electro-Communications
Takahiro Katagiri , The University of Electro-Communications; PRESTO, Japan Science and Technology Agency (JST)
Kenji Kise , The University of Electro-Communications; PRESTO, Japan Science and Technology Agency (JST)
pp. 10-19

Power-Aware Register Renaming in High-Performance Processors Power-Aware Register Renaming in High-Performance Processors (Abstract)

Alexander Veidenbaum , University of California, Irvine
Marisa L?pez-Vallejo , Universidad Polit?cnica de Madrid, Spain
Jos? L. Ayala , Universidad Polit?cnica de Madrid, Spain
pp. 20-27
Parallel Processing

Custom-Enabled System Architectures for High End Computing (Abstract)

Thomas Sterling , California Institute of Technology
Peter Kogge , University of Notre Dame
pp. 30-39

A New Memory Module for COTS-Based Personal Supercomputing (Abstract)

Hideharu Amano , Keio University
Yasunori Dohi , Yokohama National University
Noboru Tanabe , Toshiba
Masasige Nakatake , Yokohama National University
Hirotaka Hakozaki , Yokohama National University
Hironori Nakajo , Tokyo University of Agriculture and Technology
pp. 40-48

Fault-Tolerant Adaptive Deadlock-Recovery Routing for k-ary n-cube Networks (Abstract)

Masahiro Sowa , University of Electro-Communications, Japan
Hiroyuki Hosogoshi , University of Electro-Communications, Japan
Tsutomu Yoshinaga , University of Electro-Communications, Japan
pp. 49-58

GXP : An Interactive Shell for the Grid Environment (Abstract)

Kenjiro Taura , University of Tokyo/JST
pp. 59-67
Compilers

Array Data Dependence Testing with the Chains of Recurrences Algebra (Abstract)

Kyle A. Gallivan , Florida State University
Robert A. van Engelen , Florida State University
Johnnie Birch , Florida State University
pp. 70-81

Memory Management for Data Localization on OSCAR Chip Multiprocessor (Abstract)

Hirofumi Nakano , Waseda University, Japan
Keiji Kimura , Waseda University, Japan
Hironori Kasahara , Waseda University, Japan
Takeshi Kodaka , Waseda University, Japan
pp. 82-88
Applications

Large-Scale 3-D Fluid Simulations for Implosion Hydrodynamics on the Earth Simulator (Abstract)

Hitoshi Murai , Japan Marine Science and Technology Center, Japan
Hitoshi Sakagami , University of Hyogo, Japan
pp. 102-108

Highly Functional Memory Architecture for Large-Scale Data Applications (Abstract)

Kiyofumi Tanaka , Japan Advanced Institute of Science and Technology; PRESTO, Japan Science and Technology Agency
Tomoharu Fukawa , NEC Micro Systems, Ltd.
pp. 109-118

Parallel Processing using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor (Abstract)

Hirofumi Nakano , Waseda University, Japan
Hironori Kasahara , Waseda University, Japan
Keiji Kimura , Waseda University, Japan
Takeshi Kodaka , Waseda University, Japan
pp. 119-127
Threaded Architectures

Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor (Abstract)

Koichi Sasada , Tokyo University of Agriculture and Technology, Japan
Masanori Yamato , Tokyo University of Agriculture and Technology, Japan
Mikiko Sato , Tokyo University of Agriculture and Technology, Japan
Norito Kato , Tokyo University of Agriculture and Technology, Japan
Osamu Tujimoto , Tokyo University of Agriculture and Technology, Japan
Kaname Uchikura , Tokyo University of Agriculture and Technology, Japan
Hironori Nakajo , Tokyo University of Agriculture and Technology, Japan
Mitaro Namiki , Tokyo University of Agriculture and Technology, Japan
pp. 139-147

YAWARA: A Meta-Level Optimizing Computer System (Abstract)

Takashi Yokota , Utsunomiya University, Japan
Gaku Ishihara , Utsunomiya University, Japan
Takanobu Baba , Utsunomiya University, Japan
Fumihito Furukawa , Utsunomiya University, Japan
Kanemitsu Ootsu , Utsunomiya University, Japan
Moriyuki Saito , Utsunomiya University, Japan
pp. 148-153

Author Index (PDF)

pp. 154
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