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2010 International Workshop on Innovative Architecture for Future Generation High Performance (2003)
Kauai, HI
July 27, 2003 to July 28, 2003
ISSN: 1527-1366
ISBN: 0-7695-2019-7
TABLE OF CONTENTS

Preface (PDF)

pp. vii

Program Committee (PDF)

pp. viii
Embedded Systems/Low Power

A Comparative Analysis of Power and Energy Management Techniques in Real Embedded Applications (Abstract)

Peter M. Kogge , Univ. of Notre Dame, IN
Jeffrey Namkung , JPL (NASA), Caltech
Kanad Ghose , State University of New York at Binghamton
Nazeeh Aranki , JPL (NASA), Caltech
Arun Rodrigues , Univ. of Notre Dame, IN
N. Benny Toomarian , JPL (NASA), Caltech
pp. 2

Correlation-based Critical Path Predictors for Low Power Microprocessors (Abstract)

Toshinori Sato , Kyushu Institute of Technology, Japan
Akihiro Chiyonobu , Kyushu Institute of Technology, Japan
Itsujiro Arita , Kyushu Sangyo University, Japan
pp. 11
High-Performance Processors

Fast Context Switching by Hierarchical Task Allocation and Reconfigurable Cache (Abstract)

Kiyofumi Tanaka , Japan Advanced Institute of Science and Technology
pp. 20

Latency Tolerant Branch Predictors (Abstract)

Alex Ramirez , Universitat Polit?cnica de Catalunya, Barcelona, Spain
Oliverio J. Santana , Universitat Polit?cnica de Catalunya, Barcelona, Spain
Mateo Valero , Universitat Polit?cnica de Catalunya, Barcelona, Spain
pp. 30

Dynamically Adaptive Fetch Size Prediction for Data Caches (Abstract)

Alex Nicolau , University of California Irvine
Weiyu Tang , University of California Irvine
Alex Veidenbaum , University of California Irvine
pp. 40
Parallel Systems I

Sizing Equivalent Performing Large-Scale Systems using Modeling (Abstract)

Darren J. Kerbyson , Los Alamos National Laboratory
Adolfy Hoisie , Los Alamos National Laboratory
pp. 46

Multigrain Parallel Processing on OSCAR CMP (Abstract)

Takeshi Kodaka , Waseda University, Japan
Motoki Obata , Hitachi, Ltd., Japan
Keiji Kimura , Waseda University, Japan
Hironori Kasahara , Waseda University, Japan
pp. 56

Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs (Abstract)

Ed Upchurch , California Institute of Technology
Thomas Sterling , California Institute of Technology
Jay B. Brockman , University of Notre Dame
pp. 66
Compilers

A New Practical Array Data Dependence Analysis for Parallelizing Compilers (Abstract)

Masaaki Mineo , Wakayama University
Yoshitoshi Kunieda , Wakayama University
Shoichi Saito , Wakayama University
Tetsutaro Uehara , Kyoto University
pp. 78

Unrolling Shape for Out-of-Order Processors (Abstract)

Sato Hiroyuki , The University of Tokyo, Japan
pp. 88
Parallel Systems II

Design and Evaluation of a Fault-Tolerant Adaptive Router for Parallel Computers (Abstract)

Tsutomu Yoshinaga , University of Electro-Communications, Tokyo, Japan
Hiroyuki Hosogoshi , University of Electro-Communications, Tokyo, Japan
Masahiro Sowa , University of Electro-Communications, Tokyo, Japan
pp. 100

Prototyping on Using a DIMM Slot as a High-performance I/O Interface (Abstract)

Yoshihiro Hamada , Tokyo University of Agriculture and Technology, Japan
Hironori Nakajo , Tokyo University of Agriculture and Technology, Japan
Akihiro Mitsuhashi , Tokyo University of Agriculture and Technology, Japan
Junji Yamamoto , Hitachi, Japan
Tomohiro Kudoh , Real World Computing Partnership, Japan
Hideharu Amano , Keio University, Japan
Hideki Imashiro , Hitachi Information Technology, Japan
Noboru Tanabe , Toshiba, Japan
pp. 108

Spec-all: Aggressive Read/Write Access Speculation Method for DSM Systems (Abstract)

Takanobu Baba , Utsunomiya University, Japan
Kanemitsu Ootsu , Utsunomiya University, Japan
Takashi Yokota , Utsunomiya University, Japan
Fumihito Furukawa , Utsunomiya University, Japan
pp. 117

Author Index (PDF)

pp. 124
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