The Community for Technology Leaders
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2002)
Kohala Coast, Big Island, Hawaii
Jan. 10, 2002 to Jan. 11, 2002
ISSN: 1527-1366
ISBN: 0-7695-1635-1

Preface (PDF)

pp. vii
Power Management

Power and Performance Fitting in Nanometer Design (Abstract)

Toshinori Sato , Kyushu Institute of Technology
Takenori Koushiro , Kyushu Institute of Technology
Akihiro Chiyonobu , Kyushu Institute of Technology
Itsujiro Arita , Kyushu Institute of Technology
pp. 3

Reducing Power with an LO Instruction Cache Using History-Based Prediction (Abstract)

Weiyu Tang , University of California at Irvine
Alexander V. Veidenbaum , University of California at Irvine
Alexandru Nicolau , University of California at Irvine
pp. 11
Performance Prediction

Tight Non-Linear Loop Timing Estimation (Abstract)

Robert A. van Engelen , Florida State University
Kyle A. Gallivan , Florida State University
pp. 21

Exploring Advanced Architectures Using Performance Prediction (Abstract)

Darren J. Kerbyson , Los Alamos National Laboratory
Harvey J. Wasserman , Los Alamos National Laboratory
Adolfy Hoisie , Los Alamos National Laboratory
pp. 27

Architecture and Compiler Co-Optimization for High Performance Computing (Abstract)

Hiroshi Nakamura , University of Tokyo
Masaaki Kondo , University of Tokyo and Japan Science and Technology Corporation
Taku Ohneda , University of Tokyo
Motonobu Fujita , University of Tokyo
Shigeru Chiba , Tokyo Institute of Technology
Mitsuhisa Sato , University of Tsukuba
Taisuke Boku , University of Tsukuba
pp. 50

Preliminary Evaluation of a Binary Translation System for Multithreaded Processors (Abstract)

Kanemitsu Ootsu , Utsunomiya University
Takashi Yokota , Utsunomiya University
Takafumi Ono , Utsunomiya University
Takanobu Baba , Utsunomiya University
pp. 77
Network Processing

A Low Latency High Bandwidth Network Interface Prototype for PC Cluster (Abstract)

Noboru Tanabe , Toshiba Corporation
Yoshihiro Hamada , Tokyo University of Agriculture and Technology
Hironori Nakajo , Tokyo University of Agriculture and Technology
Hideki Imashiro , Hitachi Information Technology Co., Ltd.
Junji Yamamoto , Hitachi, Ltd.
Tomohiro Kudoh , National Institute of Advanced Industrial Science and Technology
Hideharu Amano , Keio University
pp. 87

Design and Implementation of Interrupt Packaging Mechanism (Abstract)

Kohta Nakashima , Kyushu University
Shigeru Kusakabe , Kyushu University
Hideo Taniguchi , Kyushu University
Makoto Amamiya , Kyushu University
pp. 95

A Networking Oriented Data-Driven Processor: CUE (Abstract)

Hiroaki Nishikawa , University ofTsukuba
Ryosuke Kurebayashi , University ofTsukuba
pp. 103
Author Index

Author Index (PDF)

pp. 113
95 ms
(Ver 3.3 (11022016))