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2010 International Workshop on Innovative Architecture for Future Generation High Performance (2001)
Maui, Hawaii
Jan. 18, 2001 to Jan. 19, 2001
ISBN: 0-7695-1309-3
TABLE OF CONTENTS

Preface (PDF)

pp. vi
Low-Power System Design

Cache-In-Memory (Abstract)

Jason T. Zawodny , Univ. of Notre Dame
Peter M. Kogge , Univ. of Notre Dame
pp. 0003

Power Efficient Instruction Cache for Wide-issue Processors (Abstract)

Ana-Maria Badulescu , University of California, Irvine
Alexander Veidenbaum , University of California, Irvine
pp. 0012

Power Reduction in Superscalar Datapaths Through Dynamic Bit-Slice Activation (Abstract)

Dmitry Ponomarev , State University of New York, Binghamton
Gurhan Kucuk , State University of New York, Binghamton
Kanad Ghose , State University of New York, Binghamton
pp. 0016

Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project (Abstract)

Ana Azevedo , University of California, Irvine
Radu Comnea , University of California, Irvine
Ilya Issenin , University of California, Irvine
Rajesh Gupta , University of California, Irvine
Nikil Dutt , University of California, Irvine
Alex Nicolau , University of California, Irvine
Alex Veidenbaum , University of California, Irvine
pp. 0025
Memory Hierarchy

An Approach towards an Analytical Characterization of Locality and its Portability (Abstract)

Gianfranco Bilardi , Universita di Padova
Enoch Peserico , Massachusetts Institute of Technology
pp. 0037

Pipelined Memory Hierarchies: Scalable Organizations and Application Performance (Abstract)

Gianfranco Bilardi , Universita di Padova
Kattamuri Ekanadham , T.J. Watson Research Center
Pratap Pattnaik , T.J. Watson Research Center
pp. 0045

Cache Coherence Protocol for Home Proxy Cache on RHiNET and its Preliminary Performance Estimation (Abstract)

Hironori Nakajo , Tokyo University of Agriculture and Technology
Masaaki Ishii , Tokyo University of Agriculture and Technology
Junji Yamamoto , Real World Computing Partnership
Tomohiro Kudo , Real World Computing Partnership
Tomonori Yokoyama , Keio University
Jun-ichiro Tsuchiya , Keio University
Hideharu Amano , Keio University
pp. 0053
Compilers/Operating Systems

Wrapped System Call in Communication and Execution Fusion OS: CEFOS (Abstract)

Hiroshi Nakayama , Kyushu University
Takuya Tanabayashi , Kyushu University
Makoto Amamiya , Kyushu University
pp. 0073
High-Performance Systems

Present Status of Development of the Earth Simulator (Abstract)

Mitsuo Yokokawa , Japan Atomic Energy Research Institute
pp. 0093

An Architecture of On-Chip-Memory Multi-threading Processor (Abstract)

Takanori Matsuzaki , Kyushu University
Makoto Amamiya , Kyushu University
Hiroshi Tomiyasu , University of Tsukuba
pp. 0100

Author Index (PDF)

pp. 0109
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