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Innovative Architecture for Future Generation High-Performance Processors and Systems (1998)
Maui, Hawaii
Oct. 26, 1998 to Oct. 28, 1998
ISBN: 0-7695-0125-7

First step to combining control and data speculation (PDF)

T. Sato , Toshiba Microelectronics Engineering Laboratory, Japan
pp. 53-60

Increasing the lookahead of multilevel branch prediction (PDF)

A.V. Veidenbaum , University of California Irvine
pp. 61-67

Architecture of a parallel computer Cenju-4 (PDF)

Y. Kanoh , C&C Media Research Laboratories, NEC Corporation, Japan
pp. 105-113
Measuring, Understanding, and Optimizing Application and System Performance

ASCI Application Performance and the Impact of Commodity Processor Architectural Trends (Abstract)

Olaf Lubeck , Los Alamos National Laboratory
Adolfy Hoisie , Los Alamos National Laboratory
Federico Bassetti , Los Alamos National Laboratory
Kirk Cameron , Los Alamos National Laboratory
Yong Luo , Los Alamos National Laboratory
Harvey Wasserman , Los Alamos National Laboratory
pp. 3

System Support for Dynamic Optimization of Application Performance (Abstract)

Shih-Hao Hung , University of Michigan
Edward S. Davidson , University of Michigan
pp. 7

Development of Biological and Chemical Applications on a 64-node PC Cluster (Abstract)

Yutaka Akiyama , Real World Computing Partnership
Kentaro Onizuka , Real World Computing Partnership
Tamotsu Noguchi , Real World Computing Partnership
Makoto Ando , Real World Computing Partnership
pp. 27
Prediction and Speculative Execution

A Speculative Multithreading with Selective Multi-Path Execution (Abstract)

Kanemitsu Ootsu , Utsunomiya University
Wataru Yoshinari , Utsunomiya University
Fumihito Furukawa , Utsunomiya University
Tsutomu Yoshinaga , Utsunomiya University
Takanobu Baba , Utsunomiya University
pp. 46

First Step to Combining Control and Data Speculation (Abstract)

Toshinori Sato , Toshiba Microelectronics Engineering Laboratory
pp. 53

Increasing the Lookahead of Multilevel Branch Prediction (Abstract)

Alexander V. Veidenbaum , University of California at Irvine
pp. 61
Hardware/Software Interaction in Architecture Design

New Methods for Exploiting Program Structure and Behavior in Computer Architecture (Abstract)

Amir Roth , University of Wisconsin at Madison
Gurindar S. Sohi , University of Wisconsin at Madison
pp. 71

Achieving High Performance via Co-Designed Virtual Machines (Abstract)

J.E. Smith , University of Wisconsin at Madison
Subramanya Sastry , University of Wisconsin at Madison
Timothy Heil , University of Wisconsin at Madison
Todd M. Bezenek , University of Wisconsin at Madison
pp. 77

Experiences with Java(tm) JIT Optimization (Abstract)

Aart J.C. Bik , Intel Corporation
Milind Girkar , Intel Corporation
Mohammad R. Haghighat , Intel Corporation
pp. 87

Implementation of a Non-strict Functional Programming Language V on a Threaded Architecture EARTH (Abstract)

Shigeru Kusakabe , Kyushu University
Kentaro Inenaga , Kyushu University
Makoto Amamiya , Kyushu University
Xinan Tang , University of Delaware
Andres Marquez , University of Delaware
Guang R. Gao , University of Delaware
pp. 95
Parallel System Architecture

Architecture of a Parallel Computer Cenju-4 (Abstract)

Yasushi Kanoh , NEC Corporation
Tetsuya Hirose , NEC Corporation
Masaaki Nakamura , NEC Corporation
Takeo Hosomi , NEC Corporation
Kosuke Tatsukawa , NEC Corporation
Hiroyuki Araki , NEC Corporation
Tomoyoshi Sugawara , NEC Corporation
Toshiyuki Nakata , NEC Corporation
pp. 105

cc-COMA: The Compiler-Controlled COMA as a Framework for Parallel Computing (Abstract)

Shoichi Saito , Wakayama University
Tetsutaro Uehara , Wakayama University
Kazuki Joe , Wakayama University
Yoshitoshi Kunieda , Wakayama University
pp. 114

Index of Authors (PDF)

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