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Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems (1997)
Maui, Hawaii
Oct. 22, 1997 to Oct. 24, 1997
ISBN: 0-8186-8424-0
TABLE OF CONTENTS

Models of multiprocessor computing (PDF)

D.E. Lenoski , Div. of Adv. Syst., Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 28

Technology synergy for real system performance (PDF)

C.R. Moore , IBM Corp., Austin, TX, USA
pp. 58

Future generation processors: using hierarchy and replication (PDF)

Q. Jacobsen , Dept. of Electr. & Comput. Eng., Wisconsin Univ., WI, USA
pp. 59-66

Functionally integrated systems on a chip: technologies, architectures, CAD tools, and applications (PDF)

E.A. McShane , Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
pp. 67-75

Preface (PDF)

pp. vii
Application View of Architectures

High speed serial communication in a future parallel computer architecture (PDF)

H. Nakajo , Dept. of Comput. & Syst. Eng., Kobe Univ., Japan
pp. 125-132
Application View of Architectures
Compilation Issues
Multiprocessors I
Processor Design
Systems on a Chip
Multiprocessors II

Author Index (PDF)

pp. 0140
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