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Verilog HDL Conference, IEEE International (1997)
Santa Clara, CA
Mar. 31, 1997 to May 1, 1997
ISSN: 1085-9403
ISBN: 0-8186-7955-7
TABLE OF CONTENTS

About IVC (PDF)

pp. vi
Session 1: Design Verification: Chair: Brian Erickson, Compaq Computer Corp.

Functional Verification with Completely Self-Checking Tests (Abstract)

Eugene Zhang , Juniper Networks
Einat Yogev , Cisco Systems, Inc.
pp. 2

Implementation of a PCI Bus Virtual Driver Using PLI, Named Pipes, and Signals (Abstract)

Doug Hahn , Mitsubishi Electric ITCA
Joe Russack , Mitsubishi Electric ITCA
pp. 10
Session 2: Synthesis Techniques: Chair: Yatin Trivedi, SEVA Technologies, Inc.

Pre- and postsynthesis simulation mismatches (Abstract)

H. Howe , Cadence Design Syst. Inc., Chelmsford, MA, USA
pp. 24

Synthesis support for design partitioning (Abstract)

J. Willoughby , Cadence Design Syst., USA
pp. 32
Session 3: EDA Technology: Peripheral Developments: Chair: Ronald Munoz, PairGain Technology

A Next Generation Diagnostic ATPG System Using the Verilog HDL (Abstract)

Michael L. Lynch , Naval Undersea Warfare Center, Division Newport
Steven M. Singer , Naval Air Warfare Center, Aircraft Division
pp. 56

Analog Design with Verilog-A (Abstract)

Ramana Aisola , Motorola
Dan FitzPatrick , Motorola
Ira Miller , Motorola
pp. 64
Session 4: Tools & Technology: Chair: Samir Palnitkar, Indus Consulting Services, Inc.

OMI - A Standard Model Interface for IP Delivery (Abstract)

Doug Dunlop , Alta Group of Cadence Design Systems, Inc.
Kathy McKinley , Alta Group of Cadence Design Systems, Inc.
pp. 83

HDL and integrating system-level simulation technologies (Abstract)

K. Lang , Cadence Design Syst., USA
W. Larue , Cadence Design Syst., USA
E. Komp , Cadence Design Syst., USA
C. Ussery , Cadence Design Syst., USA
K. McKinley , Cadence Design Syst., USA
pp. 91

Author Index (PDF)

pp. 99
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