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Verilog HDL Conference, IEEE International (1996)
Santa Clara, CA
Mar. 26, 1996 to Mar. 28, 1996
ISSN: 1085-9403
ISBN: 0-8186-7429-6
TABLE OF CONTENTS
Session 1: Simulation Architectures and Language Interfaces: Chair: Mike Baird, Sylvan Technology, Inc.

The Verilog Procedural Interface for the Verilog Hardware Description Language (Abstract)

D. Roberts , Cadence Design Syst. Inc., San Jose, CA, USA
S.K. Pattanam , Cadence Design Syst. Inc., San Jose, CA, USA
C. Dawson , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 17
Session 2: Tools and Methodology: Chair: Ron Munoz, Alcatel Network Systems

VIP: a Verilog Interpreter for Preprocessing (Abstract)

S. Mittra , WIPRO Infotech. Ltd., Bangalore, India
pp. 34

Multi-methodology design: an experimental comparison (Abstract)

H. Kobayashi , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
R. Prasad , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 45
Session 3: Simulation and Synthesis Techniques: Chair: Yatin Trivedi, SEVA Technologies, Inc.

Towards a formal model of hardware synthesized from Verilog (Abstract)

J. Cowles , Wyoming Univ., Laramie, WY, USA
J. Cupal , Wyoming Univ., Laramie, WY, USA
F. Engineer , Wyoming Univ., Laramie, WY, USA
M. Arnold , Wyoming Univ., Laramie, WY, USA
A. Wallace , Wyoming Univ., Laramie, WY, USA
pp. 60

Synthesizing multi-phase HDL programs (Abstract)

Szu-Tsung Cheng , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 67

A sockets-based implementation of hardware and software co-design (Abstract)

A. Herbert , Dept. of Res. & Dev., Credence Syst. Corp., Fremont, CA, USA
pp. 77

LEAH: an introduction to behavioral abstraction and co-simulation using Perl and Verilog (Abstract)

E. Mednick , Data General Corp., USA
K. Dorman , Data General Corp., USA
B. Gelinas , Data General Corp., USA
pp. 81
Session 4: Design Validation and Verification: Chair: Samir Palnitkar, Indus Consulting Services, Inc.

Formal verification-a viable alternative to simulation? (Abstract)

A. Nordstrom , Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
pp. 90

Addressing the systems-in-silicon verification challenge: a new approach to logic verification (Abstract)

D. Kelf , Cadence Design Syst. Inc., San Jose, CA, USA
S. Caplow , Cadence Design Syst. Inc., San Jose, CA, USA
M. Sottak , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 96

Hierarchical test coverage (Abstract)

A. Herbert , Dept. of Res. & Dev., Credence Syst. Corp., Freemont, CA, USA
pp. 101

ASIC design validation in a system context (Abstract)

J. Bartlett , Sylvan Technol. Inc., USA
pp. 105

Author Index (PDF)

pp. 113
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