Information Technology: New Generations, Third International Conference on (2012)
Las Vegas, Nevada USA
Apr. 16, 2012 to Apr. 18, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITNG.2012.110
Sound rendering applications are data-intensive and memory-intensive as a sound space increases. To speed up computation and extend the simulated area, a sound rendering system based on the two-dimensional Digital Huygens Model (DHM) with timing sharing architecture is designed and implemented by a Field Programmable Gate Array (FPGA) chip XC5VLX330T. Compared with the DHM system with the traditional parallel architecture, the proposed system implemented by a FPGA chip extends about 20 times in simulated area, and speeds up 1.47 times against the software simulation carried out in a computer with an AMD Phenom 9500 Quad-core processor (2.2 GHz) and 4GB RAM. The system is relatively easy to cascade many FPGA chips to work in parallel in real applications.
timing-sharing, sound rendering, digital Huygens' model, FPGA
M. Otani et al., "Design of a FPGA-based Timing Sharing Architecture for Sound Rendering Applications," 2012 Ninth International Conference on Information Technology: New Generations (ITNG), Las Vegas, NV, 2012, pp. 484-489.