The Community for Technology Leaders
2014 IEEE International Test Conference (ITC) (2014)
Seattle, WA, USA
Oct. 20, 2014 to Oct. 23, 2014
ISBN: 978-1-4799-4722-5
TABLE OF CONTENTS

Front cover (PDF)

pp. c1

Title page (PDF)

pp. i

Copyright page (PDF)

pp. ii

Table of contents (PDF)

pp. iii-xiv

Welcome message (PDF)

Michael Purtell , Integrated Device Technology, USA
Subhasish Mitra , Stanford University, USA
pp. 1-2

Process defect trends and strategic test gaps (Abstract)

Paul G Ryan , Intel Corporation, Santa Clara, California, USA
Irfan Aziz , Intel Corporation, Santa Clara, California, USA
William B Howell , Intel Corporation, Santa Clara, California, USA
Teresa K Janczak , Intel Corporation, Santa Clara, California, USA
Davia J Lu , Intel Corporation, Santa Clara, California, USA
pp. 1-8

On the testing of hazard activated open defects (Abstract)

Chao Han , Department of Electrical and Computer Engineering, Auburn University, AL, 36849, USA
Adit D. Singh , Department of Electrical and Computer Engineering, Auburn University, AL, 36849, USA
pp. 1-6

Protecting against emerging vmin failures in advanced technology nodes (Abstract)

J. K. Jerry Lee , Cisco Systems, Inc., USA
Amr Haggag , Freescale Semiconductor, Inc., USA
William Eklow , Cisco Systems, Inc., USA
pp. 1-7

Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals (Abstract)

Nicholas L. Tzou , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Debesh Bhatta , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
pp. 1-10

Analog fault models: Back to the future? (PDF)

Mani Soma , University of Washington, USA
pp. 1

Practical random sampling of potential defects for analog fault simulation (Abstract)

Stephen Sunter , Mentor Graphics, Ottawa, Canada
Krzysztof Jurga , Mentor Graphics, Poznan, Poland
Peter Dingenen , ON Semiconductor, Belgium
Ronny Vanhooren , ON Semiconductor, Belgium
pp. 1-10

Microgrids as a resiliency resource (PDF)

Kevin Schneider , Pacific Northwest National Laboratory, USA
pp. 1

Collaboration and teamwork obstacles (PDF)

Wesley Smith , Galaxy Semiconductor, USA
pp. 1

Efficient testing of hierarchical core-based SOCs (Abstract)

B. Keller , Cadence Design Systems, USA
K. Chakravadhanula , Cadence Design Systems, USA
B. Foutz , Cadence Design Systems, USA
V. Chickermane , Cadence Design Systems, USA
A. Garg , Cadence Design Systems, Noida, India
R. Schoonover , Cadence Design Systems, USA
J. Sage , Cadence Design Systems, USA
D. Pearl , Cadence Design Systems, USA
T. Snethen , Cadence Design Systems, USA
pp. 1-10

Isometric test compression with low toggling activity (Abstract)

A. Kumar , University of Iowa, 52242, USA
M. Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
E. Moghaddam , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
S.M. Reddy , University of Iowa, 52242, USA
J. Tyszer , Poznań University of Technology, 60-965, Poland
C. Wang , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 1-7

Achieving extreme scan compression for SoC Designs (Abstract)

Peter Wohl , Synopsys, Inc., USA
John A. Waicukauski , Synopsys, Inc., USA
Jonathon E. Colburn , NVIDIA Corp., USA
Milind Sonawane , NVIDIA Corp., USA
pp. 1-8

Mitigating voltage droop during scan with variable shift frequency (Abstract)

John Schulze , AMD, Inc. Austin, USA
Ryan Tally , AMD, Inc. Austin, USA
pp. 1-8

At-speed capture power reduction using layout-aware granular clock gate enable controls (Abstract)

R. Shaikh , Texas Instruments, Bangalore, India
P. Wilson , Texas Instruments, Bangalore, India
K. Agarwal , Texas Instruments, Bangalore, India
H. V. Sanjay , Texas Instruments, Bangalore, India
R. Tiwari , Texas Instruments, Bangalore, India
K. Lath , Texas Instruments, Bangalore, India
S. Ravi , Texas Instruments, Bangalore, India
pp. 1-10

Fast BIST of I/O Pin AC specifications and inter-chip delays (Abstract)

Stephen Sunter , Mentor Graphics, Ottawa, Canada
Saghir A. Shaikh , Broadcom, San Diego, USA
Qing Lin , Broadcom, San Jose, USA
pp. 1-8

Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screening (Abstract)

Andreas Kux , Infineon Technologies AG, Neubiberg, Germany
Rudolf Ullmann , Infineon Technologies AG, Neubiberg, Germany
Thomas Kern , Infineon Technologies AG, Neubiberg, Germany
Roland Strunz , Infineon Technologies AG, Neubiberg, Germany
Hanno Melzner , Infineon Technologies AG, Neubiberg, Germany
Stephan Beuven , Infineon Technologies Dresden GmbH, Germany
Andreas Haase , Infineon Technologies Dresden GmbH, Germany
pp. 1-7

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills (Abstract)

Masahiro Ishida , Advantest Corporation, Meiwa-machi, Gunma, 370-0718, JAPAN
Takashi Kusaka , Advantest Corporation, Meiwa-machi, Gunma, 370-0718, JAPAN
Toru Nakura , VLSI Design and Education Center, the University of Tokyo, 113-0032, JAPAN
Satoshi Komatsu , VLSI Design and Education Center, the University of Tokyo, 113-0032, JAPAN
Kunihiro Asada , VLSI Design and Education Center, the University of Tokyo, 113-0032, JAPAN
pp. 1-10

Low-cost phase noise testing of complex RF ICs using standard digital ATE (Abstract)

Stephane David-Grignot , LIRMM, CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Cedex, France
Florence Azais , LIRMM, CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Cedex, France
Laurent Latorre , LIRMM, CNRS/Univ. Montpellier 2, 161 rue Ada, 34392 Cedex, France
Francois Lefevre , NXP Semiconductors - Caen, 2 Esplanade Anton Phillips, 14000, France
pp. 1-9

A novel RF self test for a combo SoC on digital ATE with multi-site applications (Abstract)

Chun-Hsien Peng , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
ChiaYu Yang , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Adonis Tsu , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Chung-Jin Tsai , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Yosen Chen , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
C.-Y. Lin , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Kai Hong , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Kaipon Kao , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Paul Liang , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
C.-L. Tsai , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
Charles Chien , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
H.-C. Hwang , MediaTek Inc., Hsinchu, Taiwan, R.O.C.
pp. 1-8

Low-distortion signal generation for ADC testing (Abstract)

Fumitaka Abe , Division of Electronics and Informatics, Gunma University, Kiryu, 376-8515 Japan
Yutaro Kobayashi , Division of Electronics and Informatics, Gunma University, Kiryu, 376-8515 Japan
Kenji Sawada , Division of Electronics and Informatics, Gunma University, Kiryu, 376-8515 Japan
Keisuke Kato , Division of Electronics and Informatics, Gunma University, Kiryu, 376-8515 Japan
Osamu Kobayashi , Semiconductor Technology Academic Research Center (STARC), Yokohama 222-0033 Japan
Haruo Kobayashi , Division of Electronics and Informatics, Gunma University, Kiryu, 376-8515 Japan
pp. 1-10

A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers (Abstract)

Myeong-Jae Park , Department of Electrical and Computer Engineering, Inter-university Semiconductor Research Center, Seoul National University, Korea
Jaeha Kim , Department of Electrical and Computer Engineering, Inter-university Semiconductor Research Center, Seoul National University, Korea
pp. 1-6

Top ten challenges in Big Data security and privacy (PDF)

Praveen K. Murthy , Fujitsu Laboratories of America, USA
pp. 1

Software in a hardware view: New models for HW-dependent software in SoC verification and test (Abstract)

Carlos Villarraga , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Bernard Schmidt , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Binghao Bao , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Rakesh Raman , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Christian Bartsch , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Thomas Fehmel , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Dominik Stoffel , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
Wolfgang Kunz , Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany
pp. 1-9

The importance of DFX, a foundry perspective (Abstract)

Saman Adham , TSMC Canada, Ottawa, Ontario, Canada
Jonathan Chang , TSMC, Hsinchu, Taiwan
H.J. Liao , TSMC, Hsinchu, Taiwan
John Hung , TSMC, Hsinchu, Taiwan
Ting-Hua Hsieh , TSMC, Hsinchu, Taiwan
pp. 1-6

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface (Abstract)

Erik Jan Marinissen , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Bart De Wachter , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Ken Smith , Cascade Microtech, Inc., 9100 SW Gemini Drive, Beaverton, OR 97008, United States of America
Jorg Kiesewetter , Cascade Microtech GmbH, Süss Straße 1, Thiendorf 01561, Germany
Mottaqiallah Taouil , Technische Universiteit Delft, Dept. of Computer Engineering, Mekelweg 4, 2628CD, The Netherlands
Said Hamdioui , Technische Universiteit Delft, Dept. of Computer Engineering, Mekelweg 4, 2628CD, The Netherlands
pp. 1-10

Wafer Level Chip Scale Package copper pillar probing (Abstract)

Hao Chen , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Hung-Chih Lin , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Ching-Nen Peng , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Min-Jer Wang , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
pp. 1-6

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation (Abstract)

Chen-Yong Cher , IBM Research, USA
K. Paul Muller , IBM Research, USA
Ruud A. Haring , IBM Research, USA
David L. Satterfield , IBM Research, USA
Thomas E. Musta , IBM Research, USA
Thomas M. Gooding , IBM Research, USA
Kristan D. Davis , IBM Research, USA
Marc B. Dombrowa , IBM Research, USA
Gerard V. Kopcsay , IBM Research, USA
Robert M. Senger , IBM Research, USA
Yutaka Sugawara , IBM Research, USA
Krishnan Sugavanam , IBM Research, USA
pp. 1-6

Efficient RAS support for die-stacked DRAM (Abstract)

Hyeran Jeon , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA
Gabriel H. Loh , AMD Research, Advanced Micro Devices, Inc., Bellevue, WA, USA
Murali Annavaram , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA
pp. 1-10

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC (Abstract)

Rajesh Mittal , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Mudasir Kawoosa , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Rubin A. Parekhji , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
pp. 1-9

Robustness of TAP-based scan networks (Abstract)

Farrokh Ghani Zadegan , Lund University, Sweden
Gunnar Carlsson , Ericsson AB, Stockholm, Sweden
Erik Larsson , Lund University, Sweden
pp. 1-10

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors (PDF)

Keith Bowman , Qualcomm, Raleigh, NC, USA
Alex Park , Qualcomm, San Diego, CA, USA
Venkat Narayanan , Qualcomm, San Diego, CA, USA
Francois Atallah , Qualcomm, Raleigh, NC, USA
Alain Artieri , Qualcomm, San Diego, CA, USA
Sei Seung Yoon , Qualcomm, San Diego, CA, USA
Kendrick Yuen , Qualcomm, San Diego, CA, USA
David Hansquine , Qualcomm, Raleigh, NC, USA
pp. 1

A Tag based solution for efficient utilization of efuse for memory repair (Abstract)

Harsharaj Ellur , Texas Instruments, Inc. Bangalore, India
Kalpesh Shah , Texas Instruments, Inc. Bangalore, India
pp. 1-7

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation (Abstract)

Ali Ahmadi , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
Ke Huang , Department of Electrical and Computer Engineering, San Diego State University, CA 92115, USA
Suriyaprakash Natarajan , Intel Corp., 2200 Mission College Boulevard, Santa Clara, CA 95054, USA
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
pp. 1-10

Yield optimization using advanced statistical correlation methods (Abstract)

Jeff Tikkanen , University of California, Santa Barbara, USA
Sebastian Siatkowski , University of California, Santa Barbara, USA
Nik Sumikawa , Freescale Semiconductor, USA
Li-C. Wang , University of California, Santa Barbara, USA
Magdy S. Abadir , University of California, Santa Barbara, USA
pp. 1-10

Big data and test (PDF)

Anne Gattiker , IBM, USA
pp. 1

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling (Abstract)

Shanghang Zhang , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
Xin Li , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
R. D. Blanton , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
Jose Machado da Silva , INESC TEC, Faculdade de Engenharia, Universidade do Porto, 4200-465, Portugal
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, Dallas, 75243, USA
Kenneth M. Butler , Texas Instruments Inc., 12500 TI Boulevard, Dallas, 75243, USA
pp. 1-10

IC laser trimming speed-up through wafer-level spatial correlation modeling (Abstract)

Constantinos Xanthopoulos , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
Ke Huang , Department of Electrical and Computer Engineering, San Diego State University, CA 92115, USA
Abbas Poonawala , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Amit Nahar , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Bob Orr , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
pp. 1-7

Design and test of analog circuits towards sub-ppm level (Abstract)

Georges Gielen , ESAT-MICAS, Dept. Electrical Engineering, KU Leuven, Belgium
Wim Dobbelaere , ON Semiconductor, Oudenaarde, Belgium
Ronny Vanhooren , ON Semiconductor, Oudenaarde, Belgium
Anthony Coyette , ESAT-MICAS, Dept. Electrical Engineering, KU Leuven, Belgium
Baris Esen , ESAT-MICAS, Dept. Electrical Engineering, KU Leuven, Belgium
pp. 1-2

Redundancy architectures for channel-based 3D DRAM yield improvement (Abstract)

Bing-Yang Lin , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Wan-Ting Chiang , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Mincent Lee , Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
Hung-Chih Lin , Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
Ching-Nen Peng , Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
Min-Jer Wang , Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
pp. 1-7

Vesuvius-3D: A 3D-DfT demonstrator (Abstract)

Erik Jan Marinissen , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Bart De Wachter , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Stephen O'Loughlin , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Sergej Deutsch , Cadence Design Systems, Mozartstraße 2, D-85622 Feldkirchen, Germany
Christos Papameletis , Cadence Design Systems, Mozartstraße 2, D-85622 Feldkirchen, Germany
Tobias Burgherr , Cadence Design Systems, Mozartstraße 2, D-85622 Feldkirchen, Germany
pp. 1-10

A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs (Abstract)

Mukesh Agrawal , Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA
Bill Eklow , Cisco Systems, San Jose, CA 95134, USA
pp. 1-10

Knowledge discovery and knowledge transfer in board-level functional fault diagnosis (Abstract)

Fangming Ye , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Zhaobo Zhang , Huawei Technologies Co. Ltd., San Jose, CA, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Xinli Gu , Huawei Technologies Co. Ltd., San Jose, CA, USA
pp. 1-10

Board manufacturing test correlation to IC manufacturing test (Abstract)

C. Glenn Shirley , ECE, Portland State University, OR, USA
W. Robert Daasch , ECE, Portland State University, OR, USA
Phil Nigh , IBM Inc., USA
Zoe Conroy , Cisco Systems, Inc., USA
pp. 1-8

On-chip constrained random stimuli generation for post-silicon validation using compact masks (Abstract)

Xiaobing Shi , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada
pp. 1-10

Clustering-based failure triage for RTL regression debugging (Abstract)

Zissis Poulos , Dept. of ECE, University of Toronto, Canada
Andreas Veneris , Dept. of ECE, University of Toronto, Canada
pp. 1-10

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time (Abstract)

Bruce Querbach , Intel Corporation, USA
Rahul Khanna , Intel Corporation, USA
David Blankenbeckler , Intel Corporation, USA
Yulan Zhang , Intel Corporation, USA
Ronald T Anderson , Intel Corporation, USA
David G Ellis , Intel Corporation, USA
Zale T Schoenborn , Intel Corporation, USA
Sabyasachi Deyati , Georgia Tech, USA
Patrick Chiang , Oregon State University, USA
pp. 1-10

Analytical MRAM test (Abstract)

Raphael Robertazzi , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Janusz Nowak , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Jonathan Sun , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
pp. 1-10

Read disturb fault detection in STT-MRAM (Abstract)

Rajendra Bishnoi , Karlsruhe Institute of Technology, Germany
Mojtaba Ebrahimi , Karlsruhe Institute of Technology, Germany
Fabian Oboril , Karlsruhe Institute of Technology, Germany
Mehdi B. Tahoori , Karlsruhe Institute of Technology, Germany
pp. 1-7

Intra-die process variation aware anomaly detection in FPGAs (Abstract)

Youngok Pino , University of Southern California, Information Sciences Institute, Arlington, VA, USA
Vinayaka Jyothi , University of Southern California, Information Sciences Institute, Arlington, VA, USA
Matthew French , University of Southern California, Information Sciences Institute, Arlington, VA, USA
pp. 1-6

Feature engineering with canonical analysis for effective statistical tests screening test escapes (Abstract)

Fan Lin , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Chun-Kai Hsu , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
pp. 1-10

Logic characterization vehicle design for maximal information extraction for yield learning (Abstract)

R. D. Blanton , Advanced Chip Testing Laboratory, ECE Department, Carnegie Mellon University, USA
Ben Niewenhuis , Advanced Chip Testing Laboratory, ECE Department, Carnegie Mellon University, USA
Carl Taylor , Advanced Chip Testing Laboratory, ECE Department, Carnegie Mellon University, USA
pp. 1-10

EAGLE: A regression model for fault coverage estimation using a simulation based metric (Abstract)

Shahrzad Mirkhani , Computer Engineering Research Center, 201 E 24th Street, 78712, The University of Texas at Austin, USA
Jacob A. Abraham , Computer Engineering Research Center, 201 E 24th Street, 78712, The University of Texas at Austin, USA
pp. 1-10

Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns (Abstract)

Sankar Gurumurthy , Advanced Micro Devices, Inc., Austin, Tex., USA
Mustansir Pratapgarhwala , Advanced Micro Devices, Inc., Austin, Tex., USA
Curtis Gilgan , Advanced Micro Devices, Inc., Austin, Tex., USA
Jeff Rearick , Advanced Micro Devices, Inc., Fort Collins, Colo., USA
pp. 1-8

Fault sharing in a copy-on-write based ATPG system (Abstract)

X. Cai , Synopsys, Inc. Mountain View, CA, USA
P. Wohl , Synopsys, Inc. Mountain View, CA, USA
D. Martin , Synopsys, Inc. Mountain View, CA, USA
pp. 1-8

Test pattern generation in presence of unknown values based on restricted symbolic logic (Abstract)

Dominik Erb , University of Freiburg, Georges-Köhler-Allee 51, 79110, Germany
Karsten Scheibler , University of Freiburg, Georges-Köhler-Allee 51, 79110, Germany
Michael A. Kochte , University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
Matthias Sauer , University of Freiburg, Georges-Köhler-Allee 51, 79110, Germany
Hans-Joachim Wunderlich , University of Freiburg, Georges-Köhler-Allee 51, 79110, Germany
Bernd Becker , University of Freiburg, Georges-Köhler-Allee 51, 79110, Germany
pp. 1-10

Efficient SAT-based ATPG techniques for all multiple stuck-at faults (Abstract)

Masahiro Fujita , University of Tokyo, Japan
Alan Mishchenko , University of California, Berkeley, USA
pp. 1-10

Testing silicon TV tuners on ATE without TV signal generator (Abstract)

Y. Fan , Silicon Labs, 400 West Cesar Chavez St, Austin, TX 78701 USA
A. Verma , Silicon Labs, 400 West Cesar Chavez St, Austin, TX 78701 USA
J. Janney , Silicon Labs, 400 West Cesar Chavez St, Austin, TX 78701 USA
S. Kumar , Silicon Labs, 400 West Cesar Chavez St, Austin, TX 78701 USA
pp. 1-9

A self-tuning architecture for buck converters based on alternative test (Abstract)

X. Wang , Georgia Institute of Technology, USA
K. Blanchard , Texas Instruments, USA
S. Estella , Texas Instruments, USA
A. Chatterjee , Georgia Institute of Technology, USA
pp. 1-10

Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped data (Abstract)

Li Xu , Iowa State University, Ames, USA
Degang Chen , Iowa State University, Ames, USA
pp. 1-8

Board security enhancement using new locking SIB-based architectures (Abstract)

Jennifer Dworak , Southern Methodist University, Dallas, Texas, USA
Zoe Conroy , Cisco, San Jose, California, USA
Al Crouch , ASSET InterTech, Inc., Richardson, Texas, USA
John Potter , ASSET InterTech, Inc., Richardson, Texas, USA
pp. 1-10

Counterfeit IC detection using light emission (Abstract)

Peilin Song , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Franco Stellari , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Alan Weger , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
pp. 1-8

Test-mode-only scan attack and countermeasure for contemporary scan architectures (Abstract)

Samah Mohamed Saeed , New York University Polytechnic School of Engineering, USA
Sk Subidh Ali , New York University Abu Dhabi, USA
Ozgur Sinanoglu , New York University Abu Dhabi, USA
Ramesh Karri , New York University Polytechnic School of Engineering, USA
pp. 1-8

Improving test compression with scan feedforward techniques (Abstract)

Sreenivaas S. Muthyala , Computer Engineering Research Center, University of Texas, Austin, 78712, USA
Nur A. Touba , Computer Engineering Research Center, University of Texas, Austin, 78712, USA
pp. 1-10

A diagnosis-friendly LBIST architecture with property checking (Abstract)

Sarvesh Prabhu , Department of Electrical and Computer Engineering, Virginia Tech, USA
Vineeth V. Acharya , Department of Electrical and Computer Engineering, Virginia Tech, USA
Sharad Bagri , Department of Electrical and Computer Engineering, Virginia Tech, USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, USA
pp. 1-9

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects (Abstract)

Sybille Hellebrand , University of Paderborn, Warburger Str. 100, 33098, Germany
Thomas Indlekofer , University of Paderborn, Warburger Str. 100, 33098, Germany
Matthias Kampmann , University of Paderborn, Warburger Str. 100, 33098, Germany
Michael A. Kochte , University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
Chang Liu , University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
pp. 1-8

An efficient diagnosis-aware pattern generation procedure for transition faults (Abstract)

Kuen-Jong Lee , Dept. of EE, National Cheng Kung University, Taiwan
Cheng-Hung Wu , Dept. of EE, National Cheng Kung University, Taiwan
pp. 1-10

Divide and conquer diagnosis for multiple defects (Abstract)

Shih-Min Chao , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
Po-Juei Chen , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
Jing-Yu Chen , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
Po-Hao Chen , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
Ang-Feng Lin , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
James C.-M. Li , Department of Electrical Engineering, GIEE, National Taiwan University, Taipei, Taiwan
Pei-Ying Hsueh , Realtek Semiconductor Corp., Hsinchu, Taiwan
Chun-Yi Kuo , Realtek Semiconductor Corp., Hsinchu, Taiwan
Ying-Yen Chen , Realtek Semiconductor Corp., Hsinchu, Taiwan
Jih-Nung Li , Realtek Semiconductor Corp., Hsinchu, Taiwan
pp. 1-8

Massive signal tracing using on-chip DRAM for in-system silicon debug (Abstract)

Sergej Deutsch , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-10

Error prediction and detection methodologies for reliable circuit operation under NBTI (Abstract)

Julio Vazquez-Hernandez , National Institute for Astrophysics, Optics and Electronics- INAOE, Puebla-Mexico
pp. 1-10

DfST: Design for secure testability (Abstract)

Samah Mohamed Saeed , New York University Polytechnic School of Engineering, USA
pp. 1-10

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs (Abstract)

Luca Cassano , Department of Information Engineering, University of Pisa, Italy
pp. 1-10

A test probe for TSV using resonant inductive coupling (Abstract)

Rashid Rashidzadeh , Department of Electrical and Computer Engineering, University of Windsor, ON, Canada
Iftekhar Ibne Basith , Department of Electrical and Computer Engineering, University of Windsor, ON, Canada
pp. 1-10

Optimizing redundancy design for chip-multiprocessors for flexible utility functions (Abstract)

Da Cheng , Electrical Engineering Department, University of Southern California, Los Angeles, USA
Sandeep K. Gupta , Electrical Engineering Department, University of Southern California, Los Angeles, USA
pp. 1-8
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