The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2013)
Anaheim, CA, USA USA
Sept. 6, 2013 to Sept. 13, 2013
ISSN: 1089-3539
TABLE OF CONTENTS
Papers

Title page (PDF)

pp. i

Front cover (PDF)

pp. c1

Copyright page (PDF)

pp. ii

Table of contents (PDF)

pp. iii-xii

Welcome message (PDF)

Gordon Roberts , McGill University, USA
Rob Aitken , ARM, USA
pp. 1

Best paper award winners (PDF)

Z. Yu , Iowa State University, USA
D. Chen , Iowa State University, USA
pp. 4

Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges (PDF)

Pradip Bose , Department of Power- and Reliability-Aware Microarchitectures. IBM Thomas J. Watson Research Center, USA
pp. 10

VLSI testing based security metric for IC camouflaging (PDF)

Jeyavijayan Rajendran , Polytechnic Institute of New York University, USA
Ozgur Sinanoglu , New York University Abu Dhabi, USA
Ramesh Karri , Polytechnic Institute of New York University, USA
pp. 1-4

Practical methods for extending ATE to 40 and 50Gbps (PDF)

David C. Keezer , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Carl E. Gray , L-3Com Display Systems, Alpharetta, Georgia, USA
Te-Hui Chen , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Ashraf Majid , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
pp. 1-10

An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE (PDF)

Ming Lu , Global Application Development Center, Advantest, China
pp. 1-10

A novel test structure for measuring the threshold voltage variance in MOSFETs (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
James S. Tandon , D2T, VDEC, The University of Tokyo, Japan
Satoshi Komatsu , D2T, VDEC, The University of Tokyo, Japan
Kunihiro Asada , D2T, VDEC, The University of Tokyo, Japan
pp. 1-8

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry (PDF)

Ke Huang , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
pp. 1-4

Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitude (PDF)

Wei Gao , Broadcom Corporation, 5300 California Avenue, Irvine, 92617, USA
Chris Liu , Broadcom Corporation, 5300 California Avenue, Irvine, 92617, USA
pp. 1-7

12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit (PDF)

Yi Cai , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Liming Fang , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Ivan Chan , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Max Olsen , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Kevin Richter , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
pp. 1-8

High sensitivity test signatures for unconventional analog circuit test paradigms (PDF)

Suraj Sindia , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
Vishwani D. Agrawal , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
pp. 1-10

True non-intrusive sensors for RF built-in test (PDF)

Louay Abdallah , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
pp. 1-10

Fault modeling and diagnosis for nanometric analog circuits (PDF)

Ke Huang , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
Haralampos-G. Stratigopoulosy , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031, France
Salvador Miry , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031, France
pp. 1-10

30-Gb/s optical and electrical test solution for high-volume testing (PDF)

Daisuke Watanabe , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, Japan
Shin Masuda , ADVANTEST Laboratories Ltd., Aoba-ku, Sendai, Miyagi, Japan
Hideo Hara , ADVANTEST Laboratories Ltd., Aoba-ku, Sendai, Miyagi, Japan
Tsuyoshi Ataka , ADVANTEST Laboratories Ltd., Aoba-ku, Sendai, Miyagi, Japan
Atsushi Seki , ADVANTEST Laboratories Ltd., Aoba-ku, Sendai, Miyagi, Japan
Atsushi Ono , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, Japan
Toshiyuki Okayasu , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, Japan
pp. 1-10

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch (PDF)

Sen-Kuei Hsu , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Hao Chen , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Chung-Han Huang , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Der-Jiann Liu , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Wei-Hsun Lin , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Hung-Chih Lin , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Ching-Nen Peng , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
Min-Jer Wang , Taiwan Semiconductor Manufacturing Company, Ltd., No. 6, Creation Rd. 2, Hsinchu Science Park, Taiwan 300-77, R. O. C.
pp. 1-10

RF MEMS switches for Wide I/O data bus applications (PDF)

Michael B. Cohn , MicroAssembly Technologies Inc., 934 Marina Way South, Richmond, CA, USA, 94804
Kaosio Saechao , MicroAssembly Technologies Inc., 934 Marina Way South, Richmond, CA, USA, 94804
Michael Whitlock , MicroAssembly Technologies Inc., 934 Marina Way South, Richmond, CA, USA, 94804
Daniel Brenman , MicroAssembly Technologies Inc., 934 Marina Way South, Richmond, CA, USA, 94804
Wallace T. Tang , MicroAssembly Technologies Inc., 934 Marina Way South, Richmond, CA, USA, 94804
Robert M Proie , Army Research Laboratory, 2800 Powder Mill Rd Adelphi, MD 20783, USA
pp. 1-8

Predicting system-level test and in-field customer failures using data mining (PDF)

Harry H. Chen , MediaTek Inc. Hsinchu, Taiwan
Roger Hsu , MediaTek Inc. Hsinchu, Taiwan
PaulYoung Yang , MediaTek Inc. Hsinchu, Taiwan
J. J. Shyr , MediaTek Inc. Hsinchu, Taiwan
pp. 1-10

A pattern mining framework for inter-wafer abnormality analysis (PDF)

Nik Sumikawa , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Magdy S. Abadir , Freescale Semiconductor, Inc., USA
pp. 1-10

Adaptive testing - Cost reduction through test pattern sampling (PDF)

Matt Grady , IBM Microelectronics, Essex Junction, VT, USA
Bradley Pepper , IBM Microelectronics, Essex Junction, VT, USA
Joshua Patch , IBM Microelectronics, Essex Junction, VT, USA
Michael Degregorio , IBM Microelectronics, Essex Junction, VT, USA
Phil Nigh , IBM Microelectronics, Essex Junction, VT, USA
pp. 1-8

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study (PDF)

Sandeep Kumar Goel , TSMC, San Jose, CA, USA
Saman Adham , TSMC, Ottawa, ON, Canada
Min-Jer Wang , TSMC, Hsinchu, Taiwan, R.O.C
Ji-Jan Chen , TSMC, Hsinchu, Taiwan, R.O.C
Tze-Chiang Huang , TSMC, San Jose, CA, USA
Ashok Mehta , TSMC, San Jose, CA, USA
Frank Lee , TSMC, Hsinchu, Taiwan, R.O.C
Vivek Chickermane , Cadence Design Systems, Endicott, NY, USA
Brion Keller , Cadence Design Systems, Endicott, NY, USA
Thomas Valind , Cadence Design Systems, Endicott, NY, USA
Subhasish Mukherjee , Cadence Design Systems, Noida, UP, India
Navdeep Sood , Cadence Design Systems, Noida, UP, India
Jeongho Cho , SK hynix, Icheon-si, Gyeonggi-do, Korea
Hayden Hyungdong Lee , SK hynix, Icheon-si, Gyeonggi-do, Korea
Jungi Choi , SK hynix, Icheon-si, Gyeonggi-do, Korea
Sangdoo Kim , SK hynix, Icheon-si, Gyeonggi-do, Korea
pp. 1-10

Fault diagnosis of TSV-based interconnects in 3-D stacked designs (PDF)

J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Tyszer , Poznan University of Technology, 60-965, Poland
pp. 1-9

EDT bandwidth management - Practical scenarios for large SoC designs (PDF)

J. Janicki , Poznan University of Technology, 60-965, Poland
J. Tyszer , Poznan University of Technology, 60-965, Poland
W.-T. Cheng , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Y. Huang , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
M. Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Y. Dong , Advanced Micro Devices Inc., Sunnyvale, CA 94088, USA
G. Giles , Advanced Micro Devices Inc., Sunnyvale, CA 94088, USA
pp. 1-10

A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs (PDF)

Mukesh Agrawal , Department of Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical & Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-10

Two-level compression through selective reseeding (PDF)

P. Wohl , Synopsys, Inc., USA
J.A. Waicukauski , Synopsys, Inc., USA
F. Neuveux , Synopsys, Inc., USA
G.A. Maston , Synopsys, Inc., USA
N. Achouri , Synopsys, Inc., USA
J.E. Colburn , NVIDIA Corp., USA
pp. 1-10

SmartScan - Hierarchical test compression for pin-limited low power designs (PDF)

K. Chakravadhanula , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Endicott, NY, USA
V. Chickermane , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Endicott, NY, USA
D. Pearl , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Endicott, NY, USA
A. Garg , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Noida, UP, India
R. Khurana , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Noida, UP, India
S. Mukherjee , Encounter Test R&D, Front End Design Group, Cadence Design Systems, Noida, UP, India
P. Nagaraj , Encounter Test R&D, Front End Design Group, Cadence Design Systems, San Jose, CA, USA
pp. 1-9

Differential scan-path: A novel solution for secure design-for-testability (PDF)

S. Manich , Universitat Politècnica de Catalunya - BarcelonaTech, Spain
Markus S. Wamser , Technische Universität München - TUM, Germany
Oscar M. Guillen , Technische Universität München - TUM, Germany
G. Sigl , Technische Universität München - TUM, Germany
pp. 1-9

Test data analytics — Exploring spatial and test-item correlations in production test data (PDF)

Chun-Kai Hsu , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Fan Lin , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Wangyang Zhang , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, USA
Xin Li , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, USA
John M. Carulli , Texas Instruments, Dallas, 75243, USA
Kenneth M. Butler , Texas Instruments, Dallas, 75243, USA
pp. 1-10

Process monitoring through wafer-level spatial variation decomposition (PDF)

Ke Huang , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
Nathan Kupp , Department of Electrical Engineering, Yale University, New Haven, CT 06511, USA
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, 75243, USA
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, 75080, USA
pp. 1-10

Don't forget to lock your SIB: Hiding instruments using P16871 (PDF)

Jennifer Dworak , Southern Methodist University, Dallas, Texas, USA
Al Crouch , Asset InterTech, Inc., Richardson, Texas, USA
John Potter , Asset InterTech, Inc., Richardson, Texas, USA
Adam Zygmontowicz , Southern Methodist University, Dallas, Texas, USA
Micah Thornton , Southern Methodist University, Dallas, Texas, USA
pp. 1-10

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states (PDF)

Ben Niewenhuis , Advanced Chip Test Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA
R. D. Blanton , Advanced Chip Test Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA
Mudit Bhargava , Advanced Chip Test Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA
Ken Mai , Advanced Chip Test Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA
pp. 1-8

Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs (PDF)

Sergej Deutsch , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Erik Jan Marinissen , IMEC, B-3001 Leuven, Belgium
pp. 1-10

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs (PDF)

Shi-Yu Huang , Electrical Engineering Department, National Tsing Hua University, Taiwan
Li-Ren Huang , Electrical Engineering Department, National Tsing Hua University, Taiwan
Kun-Han Tsai , Silicon Test Solutions, Mentor Graphics, USA
Wu-Tung Cheng , Silicon Test Solutions, Mentor Graphics, USA
pp. 1-8

Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study (PDF)

Yanjing Li , Stanford University, CA 94305 USA
Eric Cheng , Stanford University, CA 94305 USA
Samy Makar , Stanford University, CA 94305 USA
Subhasish Mitra , Stanford University, CA 94305 USA
pp. 1-10

Fault mitigation strategies for CUDA GPUs (PDF)

Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
Giulio Gambardella , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
Ippazio Martella , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
Daniele Rolfo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
Pascal Trotta , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Italy
pp. 1-8

A functional test of 2-GHz/4-GHz RF digital communication device using digital tester (PDF)

Kiyotaka Ichiyama , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, JAPAN
Masahiro Ishida , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, JAPAN
Kenichi Nagatani , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, JAPAN
Toshifumi Watanabe , ADVANTEST Corporation, Meiwa-machi, Ora-gun, Gunma, JAPAN
pp. 1-10

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities (PDF)

Daniel Chow , Altera Corporation, San Jose, CA, USA
Masashi Shimanouchi , Altera Corporation, San Jose, CA, USA
Mike Peng Li , Altera Corporation, San Jose, CA, USA
pp. 1-8

On the generation of compact test sets (PDF)

Amit Kumar , Dept. of ECE, Univ. of Iowa, USA
Janusz Rajski , 8005 SW Boeckman Rd., Mentor Graphics, Wilsonville, USA
Sudhakar M. Reddy , Dept. of ECE, Univ. of Iowa, USA
Chen Wang , 8005 SW Boeckman Rd., Mentor Graphics, Wilsonville, USA
pp. 1-10

The implementation and application of a protocol aware architecture (PDF)

Timothy Lyons , Teradyne, Inc. North Reading, MA USA
George Conner , Teradyne, Inc. North Reading, MA USA
John Aslanian , Teradyne, Inc. North Reading, MA USA
Shawn Sullivan , Teradyne, Inc. North Reading, MA USA
pp. 1-10

Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations (PDF)

Degang Chen , Iowa State University, Ames, USA
Zhongjun Yu , Iowa State University, Ames, USA
Krunal Maniar , Texas Instruments, Tucson, AZ, USA
Mojtaba Nowrozi , Texas Instruments, Tucson, AZ, USA
pp. 1-9

A circular pipeline processing based deterministic parallel test pattern generator (PDF)

Kuen-Wei Yeh , Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
Jiun-Lang Huang , Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
pp. 1-8

Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults (PDF)

Mahesh Prabhu , Computer Engineering Research Center, University of Texas at Austin, USA
Jacob A. Abraham , Computer Engineering Research Center, University of Texas at Austin, USA
pp. 1-7

BA-BIST: Board test from inside the IC out (PDF)

Zoe Conroy , Cisco Systems Inc., 170 West Tasman Drive, San Jose, CA 95134, USA
Alfred Crouch , Asset InterTech Inc., 2001 North Central Expy., Richardson, TX 75050, USA
pp. 1

A distributed-multicore hybrid ATPG system (PDF)

X. Cai , Synopsys, Inc. Mountain View, CA, USA
P. Wohl , Synopsys, Inc. Mountain View, CA, USA
pp. 1-7

FPGA-based universal embedded digital instrument (PDF)

Joshua Ferry , Teradyne, Inc., ATE Operations - NPI Enabling Technology, North Reading, MA, USA
pp. 1-9

AgentDiag: An agent-assisted diagnostic framework for board-level functional failures (PDF)

Zelong Sun , The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Li Jiang , The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Zhaobo Zhang , Huawei Technologies, Inc., Santa Clara, CA, USA
Zhiyuan Wang , Huawei Technologies, Inc., Santa Clara, CA, USA
Xinli Gu , Huawei Technologies, Inc., Santa Clara, CA, USA
pp. 1-8

Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping (PDF)

Siva Sudani , Iowa State University, Ames, USA
Li Xu , Iowa State University, Ames, USA
Degang Chen , Iowa State University, Ames, USA
pp. 1-10

Zero-overhead self test and calibration of RF transceivers (PDF)

Afsaneh Nassery , Arizona State University, Electrical Engineering Tempe, USA
Jae Woong Jeong , Arizona State University, Electrical Engineering Tempe, USA
Sule Ozev , Arizona State University, Electrical Engineering Tempe, USA
pp. 1-9

Early-life-failure detection using SAT-based ATPG (PDF)

Matthias Sauer , University of Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Young Moon Kim , Stanford University, Departments of EE and CS, CA, USA
Jun Seomun , Samsung Electronics System LSI Division, Yongin-City, Gyeonggi-Do, Korea 446-711
Hyung-Ock Kim , Samsung Electronics System LSI Division, Yongin-City, Gyeonggi-Do, Korea 446-711
Kyung-Tae Do , Samsung Electronics System LSI Division, Yongin-City, Gyeonggi-Do, Korea 446-711
Jung Yun Choi , Samsung Electronics System LSI Division, Yongin-City, Gyeonggi-Do, Korea 446-711
Kee Sup Kim , Samsung Electronics System LSI Division, Yongin-City, Gyeonggi-Do, Korea 446-711
Subhasish Mitra , Stanford University, Departments of EE and CS, CA, USA
Bernd Becker , University of Freiburg, Georges-Köhler-Allee 051, 79110, Germany
pp. 1-10

In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers (PDF)

N. Azuma , Graduate School of System Informatics, Kobe Univ., 1-1 Rokkodai-cho, Nada-ku, Japan
T. Makita , Graduate School of System Informatics, Kobe Univ., 1-1 Rokkodai-cho, Nada-ku, Japan
S. Ueyama , Graduate School of System Informatics, Kobe Univ., 1-1 Rokkodai-cho, Nada-ku, Japan
M. Nagata , Graduate School of System Informatics, Kobe Univ., 1-1 Rokkodai-cho, Nada-ku, Japan
S. Takahashi , Renesas Mobile Corp., 2-6-2 Nippon Bldg., Ote-machi, Chiyoda-ku, Tokyo, Japan
M. Murakami , Renesas Electronics Corp., 1753 Shimonumabe, Nakahara-ku, Kawasaki, Japan
K. Hori , Renesas Electronics Corp., 1753 Shimonumabe, Nakahara-ku, Kawasaki, Japan
S. Tanaka , Tohoku Univ., 519-1176 Aoba, Aramaki, Aoba-ku, Sendai, Japan
M. Yamaguchi , Tohoku Univ., 519-1176 Aoba, Aramaki, Aoba-ku, Sendai, Japan
pp. 1-9

A design-for-reliability approach based on grading library cells for aging effects (PDF)

Senthil Arasu , Department of Electrical Eng., University of Texas at Dallas, Richardson, 75080, USA
Mehrdad Nourani , Department of Electrical Eng., University of Texas at Dallas, Richardson, 75080, USA
John M. Carulli , Analog Engineering Operations, Texas Instruments Inc., Dallas, 75243, USA
Kenneth M. Butler , Analog Engineering Operations, Texas Instruments Inc., Dallas, 75243, USA
Vijay Reddy , CMOS Reliability, Texas Instruments Inc., Dallas, 75243, USA
pp. 1-7

Representative critical-path selection for aging-induced delay monitoring (PDF)

Farshad Firouzi , Karlsruhe Institute of Technology, Germany
Fangming Ye , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
pp. 1-10

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures (PDF)

Hongyan Zhang , Embedded Systems, Karlsruhe Institute of Technology, Germany
Lars Bauer , Embedded Systems, Karlsruhe Institute of Technology, Germany
Michael A. Kochte , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Eric Schneider , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Jorg Henkel , Embedded Systems, Karlsruhe Institute of Technology, Germany
pp. 1-10

Design rule check on the clock gating logic for testability and beyond (PDF)

Kun-Han Tsai , Silicon Test Solutions, Mentor Graphics, Wilsonville Oregon USA
Shuo Sheng , Silicon Test Solutions, Mentor Graphics, Wilsonville Oregon USA
pp. 1-8

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs (PDF)

L. B. Zordan , LIRMM - Université Montpellier II / CNRS, France
A. Bosio , LIRMM - Université Montpellier II / CNRS, France
L. Dilillo , LIRMM - Université Montpellier II / CNRS, France
P. Girard , LIRMM - Université Montpellier II / CNRS, France
A. Todri , LIRMM - Université Montpellier II / CNRS, France
A. Virazel , LIRMM - Université Montpellier II / CNRS, France
N. Badereddine , Intel Mobile Communications, Sophia Antipolis, France
pp. 1-10

Towards data reliable crossbar-based memristive memories (PDF)

Amirali Ghofrani , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Miguel Angel Lastras-Montano , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
pp. 1-10

Diagnosis and Layout Aware (DLA) scan chain stitching (PDF)

Jing Ye , State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS, Beijing 100190, China
Yu Huang , University of Chinese Academy of Sciences, Beijing 100190, China
Yu Hu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS, Beijing 100190, China
Wu-Tung Cheng , University of Chinese Academy of Sciences, Beijing 100190, China
Ruifeng Guo , University of Chinese Academy of Sciences, Beijing 100190, China
Liyang Lai , University of Chinese Academy of Sciences, Beijing 100190, China
Ting-Pu Tai , University of Chinese Academy of Sciences, Beijing 100190, China
Xiaowei Li , State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS, Beijing 100190, China
Weipin Changchien , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Daw-Ming Lee , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Ji-Jan Chen , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Sandeep C. Eruvathi , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Kartik K. Kumara , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Charles Liu , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
Sam Pan , Mentor Graphics Corp., Silicon Test Solutions, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, USA
pp. 1-10

ATE test time reduction using asynchronous clock period (PDF)

Praveen Venkataramani , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
Vishwani D. Agrawal , Department of Electrical and Computer Engineering, Auburn University, AL 36849, USA
pp. 1-10
93 ms
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