The Community for Technology Leaders
2011 IEEE International Test Conference (2011)
Anaheim, CA USA
Sept. 20, 2011 to Sept. 22, 2011
ISSN: 1089-3539
ISBN: 978-1-4577-0153-5
TABLE OF CONTENTS

Power, programmability, and granularity: The challenges of ExaScale computing (PDF)

Bill Dally , Engineering, Stanford University, Chief Scientist, NVIDIA Corporation
pp. 12

A systems perspective on the R&D of industrial technology (PDF)

Jyuo-Min Shyu , President, Industrial Technology Research Institute (ITRI), Taiwan
pp. 13

Defect Oriented Testing for analog/mixed-signal devices (PDF)

Bram Kruseman , NXP Semiconductors, The Netherlands
Bratislav Tasic , NXP Semiconductors, The Netherlands
Camelia Hora , NXP Semiconductors, The Netherlands
Jos Dohmen , NXP Semiconductors, The Netherlands
Hamidreza Hashempour , NXP Semiconductors, The Netherlands
Maikel van Beurden , NXP Semiconductors, The Netherlands
Yizi Xing , NXP Semiconductors, The Netherlands
pp. 1-10

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management (PDF)

Rajesh Mittal , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Lakshmanan Balasubramanian , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Adesh Sontakke , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Harikrishna Parthasarthy , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Prakash Narayanan , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Puneet Sabbarwal , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
Rubin A. Parekhji , Texas Instruments (India) Private Limited, Bangalore, 560 093, India
pp. 1-10

Test cost reduction through performance prediction using virtual probe (Abstract)

Hsiu-Ming Chang , Univ. of California, Santa Barbara, CA, USA
Kwang-Ting Cheng , Univ. of California, Santa Barbara, CA, USA
Wangyang Zhang , Carnegie Mellon Univ., Pittsburgh, PA, USA
Xin Li , Carnegie Mellon Univ., Pittsburgh, PA, USA
K. M. Butler , Texas Instrum., Dallas, TX, USA
pp. 1-9

P-PET: Partial pseudo-exhaustive test for high defect coverage (PDF)

Abdullah Mumtaz , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
pp. 1-8

Faster-than-at-speed test for increased test quality and in-field reliability (PDF)

Tomokazu Yoneda , Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan
Keigo Hori , Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan
Michiko Inoue , Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan
pp. 1-9

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing (PDF)

Yi-Tsung Lin , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Jiun-Lang Huang , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Xiaoqing Wen , Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan
pp. 1-7

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current (PDF)

Dhruva Acharyya , Verigy Inc.
Kosuke Miyao , Verigy Inc.
David Ting , Verigy Inc.
Daniel Lam , Verigy Inc.
Robert Smith , Verigy Inc.
Pete Fitzpatrick , Verigy Inc.
Brian Buras , Verigy Inc.
John Williamson , White Eagle Consulting
pp. 1-10

Actual implementation of multi domain test: Further reduction of cost of test (PDF)

Yasuhiro Takahashi , S&S Professional Service, Verigy Japan K.K., 9-1, Takakura-cho, Hachioji, Tokyo 192-0023 Japan
Akinori Maeda , Center Of Experts, Verigy Japan K.K., 9-1, Takakura-cho, Hachioji, Tokyo 192-0023 Japan
Mitsuhiro Ogura , Manager of Center Of Experts, Verigy Japan K.K., 9-1, Takakura-cho, Hachioji, Tokyo 192-0023 Japan
pp. 1-8

Online timing variation tolerance for digital integrated circuits (PDF)

Guihai Yan , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaowei Li , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 1-10

Physically-aware analysis of systematic defects in integrated circuits (Abstract)

Wing Chiu Tam , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. D. Blanton , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1-10

Investigation into voltage and process variation-aware manufacturing test (PDF)

Urban Ingelsson , Linkoping University, Linkoping, Sweden
Bashir M. Al-Hashimi , University of Southampton, Southampon, UK
pp. 1-10

Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks (PDF)

Zhaobo Zhang , Electrical and Computer Engineering Dept., Duke University, Durham, NC
Krishnendu Chakrabarty , Electrical and Computer Engineering Dept., Duke University, Durham, NC
Zhanglei Wang , Huawei Technologies Ltd. Co., Santa Clara, CA
Zhiyuan Wang , Huawei Technologies Ltd. Co., Santa Clara, CA
Xinli Gu , Huawei Technologies Ltd. Co., Santa Clara, CA
pp. 1-9

Surviving state disruptions caused by test: A case study (PDF)

Kenneth P. Parker , Agilent Technologies Inc., Loveland, Colorado, USA
Shuichi Kameyama , Fujitsu Limited, Kawasaki, Kanagawa, Japan
David Dubberke , Intel Corporation, Hillsboro, Oregon, USA
pp. 1-8

IEEE Std 1581 — A standardized test access methodology for memory devices (PDF)

Heiko Ehrenberg , GOEPEL Electronics, 9737 Great Hills Trail, 170, Austin, TX 78759 / USA
Bob Russell , Technical Consultant, 561½ East Fifth Street, South Boston, MA 02127 / USA
pp. 1-9

Multi-site test of RF transceivers on low-cost digital ATE (PDF)

Ivo Kore , Intel Mobile Communications GmbH, Neubiberg, Germany
Ben Schuffenhauer , Intel Mobile Communications GmbH, Neubiberg, Germany
Frank Demmerle , Intel Mobile Communications GmbH, Neubiberg, Germany
Frank Neugebauer , Intel Mobile Communications GmbH, Neubiberg, Germany
Gert Pfahl , Intel Mobile Communications GmbH, Neubiberg, Germany
Dirk Rautmann , Infineon Technologies AG, Neubiberg, Germany
pp. 1-10

Wafer probe test cost reduction of an RF/A device by automatic testset minimization — A case study (Abstract)

Dragoljub Drmanac , Univ. of California, Santa Barbara, CA, USA
Li C. Wang , Univ. of California, Santa Barbara, CA, USA
pp. 1-10

Accurate signature driven power conscious tuning of RF systems using hierarchical performance models (PDF)

Aritra Banerjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Shreyas Sen , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Shyam Devarakond , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
pp. 1-9

Low power compression utilizing clock-gating (PDF)

Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070
Elham K. Moghaddam , University of Iowa, Department of ECE, Iowa City, IA 52242
Sudhakar M. Reddy , University of Iowa, Department of ECE, Iowa City, IA 52242
pp. 1-8

Partial state monitoring for fault detection estimation (PDF)

Yiwen Shi , Brown University, Providence, Rhode Island, USA
Kantapon Kaewtip , University of California, Los Angeles, California, USA
Wan-Chan Hu , MStar Semiconductor, Inc. Taiwan
Jennifer Dworak , Southern Methodist University, Dallas, Texas, USA
pp. 1-10

Logic BIST silicon debug and volume diagnosis methodology (PDF)

M. Enamul Amyeen , Intel Corporation, Hillsboro
Andal Jayalakshmi , Intel Corporation, Hillsboro
Srikanth Venkataraman , Intel Corporation, Hillsboro
Sundar V. Pathy , Intel Corporation, Hillsboro
Ewe C. Tan , Intel Corporation, Hillsboro
pp. 1-10

Generic, orthogonal and low-cost March Element based memory BIST (PDF)

Ad J. van de Goor , ComTex, Voorwillenseweg 201, 2807 CA Gouda, The Netherlands
Said Hamdioui , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands
Halil Kukner , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands
pp. 1-10

On using address scrambling to implement defect tolerance in SRAMs (PDF)

R. Alves Fonseca , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
L. Dilillo , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
A. Bosio , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université de Montpellier II / CNRS, 161, rue Ada - 34095 Montpellier Cedex 5, France
N. Badereddine , Infineon Technologies France 2600, route des Crêtes - 06560 Sophia-Antipolis, France
pp. 1-8

A fully cell-based design for timing measurement of memory (PDF)

Yi-Chung Chang , EE Dept., National Tsing Hua University, Taiwan
Shi-Yu Huang , EE Dept., National Tsing Hua University, Taiwan
Chao-Wen Tzeng , EE Dept., National Tsing Hua University, Taiwan
Jack Yao , Elite Semiconductor Memory Technology Inc., HsinChu Taiwan
pp. 1-10

Cell-aware analysis for small-delay effects and production test results from different fault models (PDF)

F. Hapke , Mentor Graphics Hamburg Germany
J. Schloeffel , Mentor Graphics Hamburg Germany
W. Redemund , Mentor Graphics Hamburg Germany
A. Glowatz , Mentor Graphics Hamburg Germany
J. Rajski , Mentor Graphics, Wilsonville, Oregon, USA
M. Reese , AMD, Inc., Austin, Texas, USA
J. Rearick , AMD, Inc., Austin, Texas, USA
J. Rivers , AMD, Inc., Austin, Texas, USA
pp. 1-8

Lithography aware critical area estimation and yield analysis (PDF)

Priyamvada Vijayakumar , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst
Vikram B. Suresh , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst
Sandip Kundu , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst
pp. 1-8

A Software-Based Self-Test methodology for on-line testing of processor caches (PDF)

G. Theodorou , Dept. of Informatics & Telecom., Univ. of Athens, Greece
N. Kranitis , Dept. of Informatics & Telecom., Univ. of Athens, Greece
A. Paschalis , Dept. of Informatics & Telecom., Univ. of Athens, Greece
D. Gizopoulos , Dept. of Informatics & Telecom., Univ. of Athens, Greece
pp. 1-10

Design-for-debug layout adjustment for FIB probing and circuit editing (Abstract)

Kuo-An Chen , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Tsung-Wei Chang , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Meng-Chen Wu , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Sonair Chen , Spirox Corporation, Hsinchu, Taiwan
pp. 1-9

End-to-end error correction and online diagnosis for on-chip networks (PDF)

Saeed Shamshiri , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
Amirali Ghofrani , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
pp. 1-10

Efficient combination of trace and scan signals for post silicon validation and debug (PDF)

Kanad Basu , Computer and Information Science and Engineering, University of Florida, Gainesville FL 32611-6120, USA
Prabhat Mishra , Computer and Information Science and Engineering, University of Florida, Gainesville FL 32611-6120, USA
Priyadarsan Patra , Post-Si Validation Architecture, Intel Corporation, USA
pp. 1-8

Analyzing ATE interconnect performance for serial links of 10 Gbps and above (PDF)

Mitchell Lin , Broadcom Corporation Irvine, CA
Tyler Tolman , Broadcom Corporation Irvine, CA
pp. 1-8

Real-time testing method for 16 Gbps 4-PAM signal interface (PDF)

Masahiro Ishida , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan
Kiyotaka Ichiyama , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan
Daisuke Watanabe , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan
Masayuki Kawabata , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan
Toshiyuki Okayasu , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718, Japan
pp. 1-10

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs (PDF)

A. M. Majid , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA
D. C. Keezer , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA
pp. 1-10

A novel scan segmentation design method for avoiding shift timing failure in scan testing (PDF)

Yuta Yamato , Fukuoka Industry Science Technology Foundation, Fukuoka, Japan
Xiaoqing Wen , Kyushu Institute of Technology, Iizuka, Japan
Michael A. Kochte , Kyushu Institute of Technology, Iizuka, Japan
Kohei Miyase , Kyushu Institute of Technology, Iizuka, Japan
Seiji Kajihara , Kyushu Institute of Technology, Iizuka, Japan
Laung-Terng Wang , SynTest Technologies, Inc, Sunnyvale, CA, USA
pp. 1-8

Test clock domain optimization for peak power supply noise reduction during scan (PDF)

Jen-Yang Wen , Lab. of Dependable Systems Graduate Inst. of Electronics Eng. National Taiwan University Taipei, Taiwan
Yu-Chuan Huang , Lab. of Dependable Systems Graduate Inst. of Electronics Eng. National Taiwan University Taipei, Taiwan
Min-Hong Tsai , Lab. of Dependable Systems Graduate Inst. of Electronics Eng. National Taiwan University Taipei, Taiwan
Kuan-Yu Liao , Lab. of Dependable Systems Graduate Inst. of Electronics Eng. National Taiwan University Taipei, Taiwan
James C.-M. Li , Lab. of Dependable Systems Graduate Inst. of Electronics Eng. National Taiwan University Taipei, Taiwan
Ming-Tung Chang , Global Unichip Cooperation Hsinchu, Taiwan
Min-Hsiu Tsai , Global Unichip Cooperation Hsinchu, Taiwan
Chih-Mou Tseng , Global Unichip Cooperation Hsinchu, Taiwan
Hung-Chun Li , Global Unichip Cooperation Hsinchu, Taiwan
pp. 1-8

State of the art low capture power methodology (PDF)

Swapnil Bahl , Technology Research and Development, STMicroelectronics India
R. Mattiuzzo , Technology Research and Development, STMicroelectronics Italy
Shray Khullar , Technology Research and Development, STMicroelectronics India
Akhil Garg , Technology Research and Development, STMicroelectronics India
S. Graniello , Technology Research and Development, STMicroelectronics Italy
Khader S. Abdel-Hafez , Synopsys Inc., 700 East Middlefield Road, Mountain View, CA 94043
Salvatore Talluto , Synopsys Inc., 700 East Middlefield Road, Mountain View, CA 94043
pp. 1-10

Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan (PDF)

Stephen Sunter , Mentor Graphics, Ottawa, Canada
Aubin Roy , Mentor Graphics, Ottawa, Canada
pp. 1-9

Hardware hooks for transition scan characterization (PDF)

Pankaj Pant , Intel Corporation, 75 Reed Road, Hudson, MA 01749
Eric Skeels , Intel Corporation, 75 Reed Road, Hudson, MA 01749
pp. 1-8

Transition test bring-up and diagnosis on UltraSPARCTM processors (PDF)

Liang-Chi Chen , Oracle Corporation, 4160 Network Circle, Santa Clara, CA 95054
Peter Dahlgren , Oracle Corporation, 4160 Network Circle, Santa Clara, CA 95054
Paul Dickinson , Oracle Corporation, 4160 Network Circle, Santa Clara, CA 95054
Scott Davidson , Oracle Corporation, 4160 Network Circle, Santa Clara, CA 95054
pp. 1-10

Optimal manufacturing flow to determine minumum operating voltage (PDF)

Sreejit Chakravarty , LSI Corporation
Binh Dang , LSI Corporation
Darcy Escovedo , LSI Corporation
A. J. Haas , LSI Corporation
pp. 1-10

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism (PDF)

J. Janicki , Poznań University of Technology, 60-965 Poznań, Poland
J. Tyszer , Poznań University of Technology, 60-965 Poznań, Poland
A. Dutta , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
M. Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
G. Mrugalski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 1-9

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores (PDF)

Manish Sharma , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070
Avijit Dutta , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070
Brady Benware , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070
Mark Kassab , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070
pp. 1-9

Techniques to improve memory interface test quality for complex SoCs (PDF)

V. R. Devanathan , Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India
Srinivas Vooka , Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India
pp. 1-10

Die-level adaptive test: Real-time test reordering and elimination (PDF)

K. R. Gotkhindikar , Integrated Circuits Design and Test Laboratory, Portland State University, Portland
W. R. Daasch , Integrated Circuits Design and Test Laboratory, Portland State University, Portland
K. M. Butler , Texas Instruments, Dallas, TX
J. M. Carulli , Texas Instruments, Dallas, TX
A. Nahar , Texas Instruments, Dallas, TX
pp. 1-10

Forward prediction based on wafer sort data — A case study (PDF)

Nik Sumikawa , Department of ECE, UC-Santa Barbara
D. Gagi Drmanac , Department of ECE, UC-Santa Barbara
Li-C. Wang , Department of ECE, UC-Santa Barbara
LeRoy Winemberg , Freescale Semiconductor, Inc.
Magdy S. Abadir , Freescale Semiconductor, Inc.
pp. 1-10

Deterministic IDDQ diagnosis using a net activation based model (PDF)

Andras Kun , Infineon Technologies AG, Neubiberg, Germany
Ralf Arnold , Infineon Technologies AG, Neubiberg, Germany
Peter Heinrich , Infineon Technologies AG, Neubiberg, Germany
Guenole Maugard , Infineon Technologies AG, Neubiberg, Germany
Huaxing Tang , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 1-10

A novel robust and accurate spectral testing method for non-coherent sampling (PDF)

Siva Sudani , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Minshun Wu , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
pp. 1-10

Application of a continuous-time level crossing quantization method for timing noise measurements (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , University of Washington, Seattle, WA
Takafumi Aoki , Graduate School of Information Science, Tohoku University, Sendai, Miyagi, Japan
Yasuo Furukawa , Advantest Corporation, Meiwa-machi, Gunma, Japan
Katsuhiko Degawa , Advantest Corporation, Meiwa-machi, Gunma, Japan
Kunihiro Asada , D2T, VDEC, University of Tokyo, Tokyo, Japan
Mohamed Abbas , D2T, VDEC, University of Tokyo, Tokyo, Japan
Satoshi Komatsu , D2T, VDEC, University of Tokyo, Tokyo, Japan
pp. 1-10

Adaptive multidimensional outlier analysis for analog and mixed signal circuits (PDF)

Ender Yilmaz , Arizona State University
Sule Ozev , Arizona State University
Kenneth M. Butler , Texas Instruments
pp. 1-8

Pre-bond probing of TSVs in 3D stacked ICs (PDF)

Brandon Noia , Duke University, Dept. Electrical and Computer Engineering, Durham, NC 27708, USA
Krishnendu Chakrabarty , Duke University, Dept. Electrical and Computer Engineering, Durham, NC 27708, USA
pp. 1-10

Evaluation of TSV and micro-bump probing for wide I/O testing (PDF)

Ken Smith , Cascade Microtech, Inc. - Beaverton, Oregon, USA
Peter Hanaway , Cascade Microtech, Inc. - Beaverton, Oregon, USA
Mike Jolley , Cascade Microtech, Inc. - Beaverton, Oregon, USA
Reed Gleason , Cascade Microtech, Inc. - Beaverton, Oregon, USA
Eric Strid , Cascade Microtech, Inc. - Beaverton, Oregon, USA
Tom Daenen , IMEC - Leuven, Belgium
Luc Dupas , IMEC - Leuven, Belgium
Bruno Knuts , IMEC - Leuven, Belgium
Erik Jan Marinissen , IMEC - Leuven, Belgium
Marc Van Dievel , IMEC - Leuven, Belgium
pp. 1-10

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base (PDF)

Chun-Chuan Chi , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Erik Jan Marinissen , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Sandeep Kumar Goel , TSMC, 2585 Junction Avenue, San Jose, CA 95134, USA
Cheng-Wen Wu , National Tsing-Hua University, Dept. Electrical Engineering, Hsinchu 30013, Taiwan, ROC
pp. 1-10
93 ms
(Ver 3.3 (11022016))