The Community for Technology Leaders
2010 IEEE International Test Conference (2010)
Austin, TX
Nov. 2, 2010 to Nov. 4, 2010
ISSN: 1089-3539
ISBN: 978-1-4244-7206-2
TABLE OF CONTENTS

Integration for innovation—Trends in test and Moore's Law (PDF)

James Truchard , CEO and Co-founder, National Instruments, USA
pp. 12

A high linearity compact timing vernier for CMOS timing generator (PDF)

Jun Kohno , Yokogawa Electric Corporation Tokyo, Japan
Tatsuro Akiyama , Yokogawa Electric Corporation Tokyo, Japan
Dai Kato , Yokogawa Electric Corporation Tokyo, Japan
Makoto Imamura , Yokogawa Electric Corporation Tokyo, Japan
pp. 1-8

Complete testing of receiver jitter tolerance (PDF)

Timothy D. Lyons , Teradyne, Inc. North Reading, MA USA
pp. 1-10

New tools and methodology for advanced parametric and defect structure test (PDF)

Raphael Robertazzi , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA.
Louis Medina , IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533, USA
Ernesto Shiling , IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533, USA
Garry Moore , IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533, USA
Ronald Geiger , IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533, USA
Jiun-Hsin Liao , IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533, USA
John Williamson , IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA.
pp. 1-10

A low-cost ATE phase signal generation technique for test applications (PDF)

Sadok Aouini , Integrated Microsystems Laboratory, McGill University, 3480 University Street, Montreal, Quebec, CANADA H3A 2A7
Kun Chuai , Integrated Microsystems Laboratory, McGill University, 3480 University Street, Montreal, Quebec, CANADA H3A 2A7
Gordon W. Roberts , Integrated Microsystems Laboratory, McGill University, 3480 University Street, Montreal, Quebec, CANADA H3A 2A7
pp. 1-10

The scan-DFT features of AMD's next-generation microprocessor core (PDF)

Mahmut Yilmaz , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Baosheng Wang , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Jayalakshmi Rajaraman , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Tom Olsen , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Kanwaldeep Sobti , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Dwight Elvey , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Jeff Fitzgerald , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Grady Giles , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
Wei-Yu Chen , Advanced Micro Devices, Inc., 1 AMD Place, Sunnyvale, California, USA
pp. 1-10

Testing the IBM Power 7™ 4 GHz eight core microprocessor (PDF)

James Crafts , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
David Bogdan , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Dennis Conti , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Donato Forlenza , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Orazio Forlenza , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
William Huott , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Mary Kusko , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Edward Seymour , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Timothy Taylor , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
Brian Walsh , IBM Burlington VT, IBM Poughkeepsie NY, IBM East Fishkill NY, IBM Austin TX, USA
pp. 1-10

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration (PDF)

Minki Cho , School of ECE, Georgia Institute of Technology, USA
Nikhil Sathe , School of ECE, Georgia Institute of Technology, USA
Arijit Raychowdhury , Circuit Research Lab, Intel Corp., USA
Saibal Mukhopadhyay , School of ECE, Georgia Institute of Technology, USA
pp. 1-9

Redundant core testing on the cell BE microprocessor (PDF)

David Iverson , IBM Microelectronics, Burlington Vermont USA
Dan Dickinson , IBM Microelectronics, Burlington Vermont USA
John Masson , IBM Microelectronics, Burlington Vermont USA
Christina Newman-LaBounty , IBM Microelectronics, Burlington Vermont USA
Daniel Simmons , IBM Microelectronics, Burlington Vermont USA
William Tanona , IBM Microelectronics, Burlington Vermont USA
pp. 1-6

BIST of I/O circuit parameters via standard boundary scan (PDF)

Stephen Sunter , Mentor Graphics, Germany
Matthias Tilmann , Renesas Electronics Europe GmbH, Germany
pp. 1-10

Clock Gate Test Points (PDF)

Narendra Devta-Prasanna , LSI Corporation, 1501 McCarthy Blvd., Milpitas CA 95035, USA
Arun Gunda , LSI Corporation, 1501 McCarthy Blvd., Milpitas CA 95035, USA
pp. 1-10

Design and test of latch-based circuits to maximize performance, yield, and delay test quality (PDF)

Kun Young Chung , DFx Group, System LSI, Samsung Electronics, Co., Ltd., Korea
Sandeep K. Gupta , Electrical Engineering - Systems, University of Southern California, USA
pp. 1-10

Testing of latch based embedded arrays using scan tests (PDF)

Fan Yang , LSI Corporation, Milpitas, CA, USA
Sreejit Chakravarty , LSI Corporation, Milpitas, CA, USA
pp. 1-10

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains (PDF)

Tom Waayers , NXP semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands
Richard Morren , NXP semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands
Xijiang Lin , Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97068, USA
Mark Kassab , Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97068, USA
pp. 1-10

Towards effective and compression-friendly test of memory interface logic (PDF)

V.R. Devanathan , Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India
Alan Hales , Texas Instruments Inc., Dallas, 75266, USA
Sumant Kale , Texas Instruments Inc., Dallas, 75266, USA
Dharmesh Sonkar , Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India
pp. 1-10

Test cycle power optimization for scan-based designs (PDF)

Kun-Han Tsai , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Yu Huang , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Ting-Pu Tai , Mentor Graphics Corp. Wilsonville, OR 97070, USA
Augusli Kifli , Faraday Technology Co. Hsinchu, Taiwan
pp. 1-10

Automated trace signals selection using the RTL descriptions (PDF)

Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 1-10

QED: Quick Error Detection tests for effective post-silicon validation (PDF)

Ted Hong , Dept. of EE, Stanford University, CA 94305 USA
Yanjing Li , Dept. of EE, Stanford University, CA 94305 USA
Sung-Boem Park , Intel Corporation, Santa Clara, CA 95054 USA
Diana Mui , Dept. of EE, Stanford University, CA 94305 USA
David Lin , Dept. of EE, Stanford University, CA 94305 USA
Ziyad Abdel Kaleq , Dept. of EE, Stanford University, CA 94305 USA
Nagib Hakim , Intel Corporation, Santa Clara, CA 95054 USA
Helia Naeimi , Intel Corporation, Santa Clara, CA 95054 USA
Donald S. Gardner , Intel Corporation, Santa Clara, CA 95054 USA
Subhasish Mitra , Dept. of EE, Stanford University, CA 94305 USA
pp. 1-10

A kernel-based approach for functional test program generation (PDF)

Po-Hsien Chang , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Jayanta Bhadra , Freescale Semiconductor, Inc., USA
pp. 1-10

Modeling TSV open defects in 3D-stacked DRAM (PDF)

Li Jiang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Yuxi Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Lian Duan , Department of Computer Science & Engineering, Pennsylvania State University, USA
Yuan Xie , Department of Computer Science & Engineering, Pennsylvania State University, USA
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 1-9

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs (PDF)

Mottaqiallah Taouil , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Said Hamdioui , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Jouke Verbree , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Erik Jan Marinissen , IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
pp. 1-10

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs (PDF)

Brandon Noia , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Erik Jan Marinissen , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 1-9

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs (PDF)

Saeed Shamshiri , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, 93106, USA
pp. 1-10

Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches (PDF)

Rudrajit Datta , Computer Engineering Research Center, The University of Texas at Austin, 78712, USA
Nur A. Touba , Computer Engineering Research Center, The University of Texas at Austin, 78712, USA
pp. 1-7

Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor (PDF)

Rance Rodrigues , University of Massachusetts at Amherst, Department of Electrical and Computer Engineering, USA
Sandip Kundu , University of Massachusetts at Amherst, Department of Electrical and Computer Engineering, USA
Omer Khan , Massachusetts Institute of Technology, Computer Science and Artificial Intelligence Lab, USA
pp. 1-10

Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers (PDF)

Koji Asami , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718 Japan
Toshiaki Kurihara , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718 Japan
Yushi Inada , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma, 370-0718 Japan
pp. 1-8

Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude (PDF)

Devin Morris , University of Florida, Gainesville, USA
William R. Eisenstadt , University of Florida, Gainesville, USA
Andrea Paganini , IBM System & Technology Group, Essex Junction, VT, USA
Mustapha Slamani , IBM System & Technology Group, Essex Junction, VT, USA
Timothy Platt , IBM System & Technology Group, Essex Junction, VT, USA
John Ferrario , IBM System & Technology Group, Essex Junction, VT, USA
pp. 1-8

Post-production performance calibration in analog/RF devices (PDF)

Nathan Kupp , Department of Electrical Engineering, Yale University, New Haven, CT 06511, USA
He Huang , Department of Electrical Engineering, Yale University, New Haven, CT 06511, USA
Petros Drineas , Department of Computer Science, Rensselaer Polytechnic Institute, Troy, NY 12180, USA
Yiorgos Makris , Department of Electrical Engineering, Yale University, New Haven, CT 06511, USA
pp. 1-10

Increasing PRPG-based compression by delayed justification (PDF)

P. Wohl , Synopsys, Inc., USA
J.A. Waicukauski , Synopsys, Inc., USA
T. Finklea , Synopsys, Inc., USA
pp. 1-10

Dynamic channel allocation for higher EDT compression in SoC designs (PDF)

M. Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
G. Mrugalski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Janicki , Poznan University of Technology, 60-965, Poland
J. Tyszer , Poznan University of Technology, 60-965, Poland
pp. 1-10

Predictive analysis for projecting test compression levels (PDF)

Ozgur Sinanoglu , Computer Engineering Department, New York University Abu Dhabi, USA
Sobeeh Almukhaizim , Computer Engineering Department, Kuwait University, Kuwait
pp. 1-10

Defect-oriented cell-internal testing (PDF)

F. Hapke , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
W. Redemund , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
J. Schloeffel , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
R. Krenz-Baath , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
A. Glowatz , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
M. Wittke , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany
H. Hashempour , NXP Semiconductors, Prof. Holstlaan, HTC-46, 5656AA Eindhoven, The Netherlands
S. Eichenberger , NXP Semiconductors, Gerstweg 2, FD3, 6534AE Nijmegen, The Netherlands
pp. 1-10

Modeling the impact of process variation on resistive bridge defects (PDF)

Saqib Khursheed , School of ECS, University of Southampton, UK
Shida Zhong , School of ECS, University of Southampton, UK
Robert Aitken , School of ECS, University of Southampton, UK
Bashir M. Al-Hashimi , ARM Limited, San Jose, CA, USA
Sandip Kundu , University of Massachusetts, Amherst, USA
pp. 1-10

Automatic classification of bridge defects (PDF)

Jeffrey E. Nelson , Center for Silicon System Implementation, Carnegie Mellon University, Pittsburgh, PA 15213, USA
Wing Chiu Tam , Center for Silicon System Implementation, Carnegie Mellon University, Pittsburgh, PA 15213, USA
R. D. Blanton , Center for Silicon System Implementation, Carnegie Mellon University, Pittsburgh, PA 15213, USA
pp. 1-10

A high density small size RF test module for high throughput multiple resource testing (PDF)

M. Kimishima , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
S. Mizuno , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
T. Seki , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
H. Takeuti , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
H. Nagami , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
H. Shirasu , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
Y. Haraguti , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Gunma, 370-0718, Japan
J. Okayasu , ADVANTEST Laboratories Ltd, 48-2, Kamiayashi, Aoba-ku, Sendai-shi, Miyagi, 989-3124, Japan
M. Nakanishi , ADVANTEST Laboratories Ltd, 48-2, Kamiayashi, Aoba-ku, Sendai-shi, Miyagi, 989-3124, Japan
pp. 1-10

RADPro: Automatic RF analyzer and diagnostic program generation tool (PDF)

Sukeshwar Kannan , University of Alabama, Tuscaloosa, USA
Bruce Kim , University of Alabama, Tuscaloosa, USA
Ganesh Srinivasan , Texas Instruments Inc., Dallas, USA
Friedrich Taenzlar , Texas Instruments Inc., Dallas, USA
Richard Antley , Texas Instruments Inc., Dallas, USA
Craig Force , Texas Instruments Inc., Dallas, USA
Falah Mohammed , AN-Najah National University, Palestine
pp. 1-9

Timing skew compensation technique using digital filter with novel linear phase condition (PDF)

Koji Asami , Advantest Corporation, Meiwa-machi, Ora-gun, Gunma 370-0718 Japan
Hiroyuki Miyajima , Dept. of Electronic Engineering, Gunma University, Kiryu, 376-8515 Japan
Tsuyoshi Kurosawa , Dept. of Electronic Engineering, Gunma University, Kiryu, 376-8515 Japan
Takenori Tateiwa , Dept. of Electronic Engineering, Gunma University, Kiryu, 376-8515 Japan
Haruo Kobayashi , Dept. of Electronic Engineering, Gunma University, Kiryu, 376-8515 Japan
pp. 1-9

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications (PDF)

Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Dawen Xu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
pp. 1-10

Highly efficient parallel ATPG based on shared memory (PDF)

X. Cai , Synopsys, Inc., USA
P. Wohl , Synopsys, Inc., USA
J.A. Waicukauski , Synopsys, Inc., USA
P. Notiyath , Synopsys, Inc., USA
pp. 1-7

A diagnostic test generation system (PDF)

Yu Zhang , Auburn University, Department of Electrical and Computer Engineering, AL 36849, USA
Vishwani D. Agrawal , Auburn University, Department of Electrical and Computer Engineering, AL 36849, USA
pp. 1-9

Mask versus Schematic - an enhanced design-verification flow for first silicon success (PDF)

Tseng-Chin Luo , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan
Eric Leong , Altera Corporation, USA
Mango C.-T. Chao , Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
Philip A. Fisher , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan
Wen-Hsiang Chang , Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
pp. 1-9

Systematic defect identification through layout snippet clustering (PDF)

Wing Chiu Tam , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
Osei Poku , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
R. D. Blanton , ECE Department, Carnegie Mellon University, Pittsburgh, PA 15213, USA
pp. 1-10

Hard to find, easy to find systematics; just find them (PDF)

Rao Desineni , 300mm Diagnostics Characterization, IBM Systems & Technology Group, Hopewell Junction, NY, USA
Leah Pastel , 300mm Diagnostics Characterization, IBM Systems & Technology Group, Essex Junction, VT., USA
Maroun Kassab , 300mm Diagnostics Characterization, IBM Systems & Technology Group, Essex Junction, VT., USA
Robert Redburn , Product Engineering, IBM Systems & Technology Group, Essex Junction, VT., USA
pp. 1-10

Structural approach for built-in tests in RF devices (PDF)

Deepa Mannath , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
Dallas Webster , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
Victor Montano-Martinez , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
David Cohen , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
Shai Kush , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
Thiagarajan Ganesan , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
Adesh Sontakke , Texas Instruments Inc., 12500 TI Blvd., Dallas, USA
pp. 1-7

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery (PDF)

Sudeep Puligundla , Intel, Hillsboro, OR, 2111 NE 25th Avenue, M.S: JF4-215, Hillsboro, 97124, USA
Fulvio Spagna , Intel, Santa Clara, CA, 2111 NE 25th Avenue, M.S: JF4-215, Hillsboro, OR - 97124, USA
Lidong Chen , Intel, Santa Clara, CA, 2111 NE 25th Avenue, M.S: JF4-215, Hillsboro, OR - 97124, USA
Amanda Tran , Intel, Santa Clara, CA, 2111 NE 25th Avenue, M.S: JF4-215, Hillsboro, OR - 97124, USA
pp. 1-5

ADC linearity testing method with single analog monitoring port (PDF)

Tomohiro Kawachi , Yokogawa Electric Corporation, Inc. Tokyo, Japan
Koichi Irie , Yokogawa Electric Corporation, Inc. Tokyo, Japan
pp. 1-8

Fault models and test methods for subthreshold SRAMs (PDF)

Chen-Wei Lin , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Hung-Hsin Chen , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Hao-Yu Yang , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Mango C.-T. Chao , Dept. of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Rei-Fu Huang , MediaTek Inc., Hsinchu, Taiwan
pp. 1-10

Detecting memory faults in the presence of bit line coupling in SRAM devices (PDF)

Sandra Irobi , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
Zaid Al-Ars , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
Said Hamdioui , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
pp. 1-10

A programmable BIST for DRAM testing and diagnosis (PDF)

P. Bernardi , Dipartimento di Automatica e Informatica - Politecnico di Torino, Italy
M. Grosso , Dipartimento di Automatica e Informatica - Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica - Politecnico di Torino, Italy
Y. Zhang , Dipartimento di Automatica e Informatica - Politecnico di Torino, Italy
pp. 1-10

Rapid FPGA delay characterization using clock synthesis and sparse sampling (PDF)

Mehrdad Majzoobi , Electrical and Computer Engineering Department, Rice University, Houston, Texas 77005, USA
Eva Dyer , Electrical and Computer Engineering Department, Rice University, Houston, Texas 77005, USA
Ahmed Elnably , Electrical and Computer Engineering Department, Rice University, Houston, Texas 77005, USA
Farinaz Koushanfar , Electrical and Computer Engineering Department, Rice University, Houston, Texas 77005, USA
pp. 1-10

Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing (PDF)

Xin He , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, 80523, USA
Yashwant Malaiya , Department of Computer Science, Colorado State University, Fort Collins, 80523, USA
Anura P. Jayasumana , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, 80523, USA
Kenneth P. Parker , Agilent Technologies, Loveland, CO 80537, USA
Stephen Hird , Agilent Technologies, Loveland, CO 80537, USA
pp. 1-10

Improving fault diagnosis accuracy by automatic test set modification (PDF)

L. Amati , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
C. Bolchini , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
F. Salice , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
F. Franzoso , Cisco Photonics, Monza, Italy
pp. 1-8

Board-level fault diagnosis using an error-flow dictionary (PDF)

Zhaobo Zhang , ECE Dept., Duke University, Durham, NC, USA
Zhanglei Wang , Cisco Systems, Inc., San Jose, CA, USA
Xinli Gu , Cisco Systems, Inc., San Jose, CA, USA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, USA
pp. 1-10

Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test (PDF)

Rosa Reinosa , Hewlett-Packard, Palo Alto, CA, USA
Aileen Allen , Hewlett-Packard, Palo Alto, CA, USA
Elizabeth Benedetto , Hewlett-Packard, Houston, TX, USA
Alan Mcallister , Intel Corporation, Portland, OR, USA
pp. 1-11

Automated test program generation for automotive devices (PDF)

Anke Drappa , Robert Bosch, GmbH, Reutlingen, Germany
Peter Huber , Teradyne, GmbH, Munich, Germany
Jon Vollmar , Teradyne, Inc., Brookfield, WI USA
pp. 1-10

STIL P1450.4: A standard for test flow specification (PDF)

Jim O'Reilly , P1450.4 Working Group, USA
Ajay Khoche , P1450.4 Working Group, USA
Ernst Wahl , P1450.4 Working Group, USA
Bruce Parnas , P1450.4 Working Group, USA
pp. 1-10

Concurrent test planning (PDF)

Bethany Van Wagenen , Teradyne, Inc., North Reading, MA, USA
Edward Seng , Teradyne, Inc., North Reading, MA, USA
pp. 1-10

Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor (PDF)

Pankaj Pant , Intel Corporation, 75 Reed Road, Hudson, MA 01749, USA
Joshua Zelman , Intel Corporation, 75 Reed Road, Hudson, MA 01749, USA
Glenn Colon-Bonet , Intel Corporation, 4721 Technology Pkwy, Fort Collins, CO 80528, USA
Jennifer Flint , Intel Corporation, 4721 Technology Pkwy, Fort Collins, CO 80528, USA
Steve Yurash , Intel Corporation, 4721 Technology Pkwy, Fort Collins, CO 80528, USA
pp. 1-8

Path coverage based functional test generation for processor marginality validation (PDF)

Suriyaprakash Natarajan , Intel Corporation, Santa Clara, CA, USA
Arun Krishnamachary , Intel Corporation, Chandler, AZ, USA
Eli Chiprout , Intel Corporation, Hillsboro, OR, USA
Rajesh Galivanche , Intel Corporation, Santa Clara, CA, USA
pp. 1-9

Mining AC delay measurements for understanding speed-limiting paths (PDF)

Janine Chen , Department of ECE, UC-Santa Barbara, USA
Brendon Bolin , Department of ECE, UC-Santa Barbara, USA
Li-C. Wang , Department of ECE, UC-Santa Barbara, USA
Jing Zeng , 2Advanced Micro Devices, Inc., USA
Dragoljub Drmanac , Department of ECE, UC-Santa Barbara, USA
Michael Mateja , 2Advanced Micro Devices, Inc., USA
pp. 1-10

Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins (PDF)

CJ Clark , Intellitech Corp, Dover, NH, USA
Dave Dubberke , Intel Corp, Hillsboro, OR, USA
Kenneth P. Parker , Agilent Technologies, Loveland, CO, USA
Bill Tuthill , Intellitech Corp, Dover, NH, USA
pp. 1-8

Surviving state disruptions caused by test: The “Lobotomy Problem” (PDF)

Kenneth P. Parker , Agilent Technologies, Loveland, Colorado, USA
pp. 1-8

Commanded Test Access Port operations (PDF)

Lee Whetse , Texas Instruments, USA
pp. 1-10

Precision audio nulling instrumentation achieves near −140dB measurements in a production environment (PDF)

Carl Karandjeff , LTX-Credence Corporation, Norwood, MA 02062 USA
Chris Hannaford , LTX-Credence Corporation, Norwood, MA 02062 USA
pp. 1-10

Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs (PDF)

Suri Basharapandiyan , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
Yi Cai , LSI, Inc, 1110 American Parkway NE, Allentown, Pennsylvania 18109, USA
pp. 1-7

Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages (PDF)

Ki-Jae Song , Test & Package Center, Samsung Electronics, South Korea
Hunkyo Seo , Test & Package Center, Samsung Electronics, South Korea
Sang-hyun Ko , Test & Package Center, Samsung Electronics, South Korea
pp. 1-9

Constrained ATPG for functional RTL circuits using F-Scan (PDF)

Marie Engelene J. Obien , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City 630-0192, Japan
Satoshi Ohtake , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City 630-0192, Japan
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City 630-0192, Japan
pp. 1-10

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage (PDF)

Alodeep Sanyal , Synopsys Inc., 700 E Middlefield Road, Mountain View, CA, USA
Krishnendu Chakrabarty , ECE Department, Duke University, Durham, NC, USA
Mahmut Yilmaz , Advanced Micro Devices Inc., 1 AMD Place, Sunnyvale, CA, USA
Hideo Fujiwara , School of Information Science, Nara Inst. of Science and Technology, Japan
pp. 1-10

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation (Abstract)

Shuou Nomura , University of Wisconsin-Madison, USA
Karthikeyan Sankaralingam , University of Wisconsin-Madison, USA
Ranganathan Sankaralingam1 , Cadence Design Systems Inc., San Jose, USA
pp. 1-10

Leveraging existing power control circuits and power delivery architecture for variability measurement (PDF)

Dhruva Acharyya , Verigy Ltd., USA
Kanak Agarwal , IBM Corp., USA
Jim Plusquellic , Dept. of Electrical and Computer Engineering, Univ. of New Mexico, USA
pp. 1-9

An on-line monitoring technique for electrode degradation in bio-fluidic microsystems (PDF)

Q. Al-Gayem , Centre for Microsystems Engineering, Lancaster University, UK
H. Liu , Moor Instruments Ltd, Axminster, UK
A. Richardson , Centre for Microsystems Engineering, Lancaster University, UK
N. Burd , Centre for Microsystems Engineering, Lancaster University, UK
M. Kumar , Centre for Microsystems Engineering, Lancaster University, UK
pp. 1-10

Estimating defect-type distributions through volume diagnosis and defect behavior attribution (PDF)

Xiaochun Yu , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, U.S.A.
R. D. Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, U.S.A.
pp. 1-10

Adaptive test flow for mixed-signal/RF circuits using learned information from device under test (PDF)

Ender Yilmaz , Arizona State University, USA
Sule Ozev , Arizona State University, USA
Kenneth M. Butler , Texas Instruments, USA
pp. 1-10

Analog neural network design for RF built-in self-test (PDF)

Dzmitry Maliuk , Electrical Engineering Department, Yale University, 10 Hillhouse Ave, New Haven, CT 06520-8267, USA
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
He Huang , Electrical Engineering Department, Yale University, 10 Hillhouse Ave, New Haven, CT 06520-8267, USA
Yiorgos Makris , Electrical Engineering Department, Yale University, 10 Hillhouse Ave, New Haven, CT 06520-8267, USA
pp. 1-10

A new method for estimating spectral performance of ADC from INL (PDF)

Jingbo Duan , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
Le Jin , National Semiconductor, Santa Clara, CA 95051, USA
Degang Chen , Department of Electrical and Computer Engineering, Iowa State University, Ames, 50011, USA
pp. 1-10

Low power compression of incompatible test cubes (PDF)

D. Czysz , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
G. Mrugalski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
P. Szczerbicki , Poznan University of Technology, 60-965, Poland
J. Tyszer , Poznan University of Technology, 60-965, Poland
pp. 1-10

Low capture power at-speed test in EDT environment (PDF)

Elham K. Moghaddam , University of Iowa, Department of ECE, 52242, USA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Sudhakar. M. Reddy , University of Iowa, Department of ECE, 52242, USA
Xijiang Lin , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Nilanjan Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 1-10

Low cost at-speed testing using On-Product Clock Generation compatible with test compression (PDF)

B. Keller , Cadence Design Systems, USA
K. Chakravadhanula , Cadence Design Systems, USA
B. Foutz , Cadence Design Systems, USA
V. Chickermane , Cadence Design Systems, USA
R. Malneedi , Cadence Design Systems, USA
T. Snethen , Cadence Design Systems, USA
V. Iyengar , IBM Corp., Burlington, Vermont, USA
D. Lackey , IBM Corp., Burlington, Vermont, USA
G. Grise , IBM Corp., Burlington, Vermont, USA
pp. 1-10

MT-SBST: Self-test optimization in multithreaded multicore architectures (PDF)

N. Foutris , University of Piraeus, Department of Informatics, Greece
M. Psarakis , University of Piraeus, Department of Informatics, Greece
D. Gizopoulos , University of Piraeus, Department of Informatics, Greece
A. Apostolakis , University of Piraeus, Department of Informatics, Greece
X. Vera , Intel Barcelona Research Center, Intel Labs-UPC, Spain
A. Gonzalez , Intel Barcelona Research Center, Intel Labs-UPC, Spain
pp. 1-10

On techniques for handling soft errors in digital circuits (PDF)

Warin Sootkaneung , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
Kewal K. Saluja , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 53706, USA
pp. 1-9

Soft error reliability aware placement and routing for FPGAs (PDF)

Mohammed A. Abdul-Aziz , Dept. of Electrical & Computer Engineering, Northeastern University, Boston, USA
Mehdi B. Tahoori , Dept. of Electrical & Computer Engineering, Northeastern University, Boston, USA
pp. 1-9

High-Volume Scan Analysis: Practical challenges and applications for industrial IC development (PDF)

Darrell Carder , Freescale Semiconductor Inc., 6501 William Cannon Drive West, Austin, TX 78735, USA
Steve Palosh , Freescale Semiconductor Inc., 6501 William Cannon Drive West, Austin, TX 78735, USA
Rajesh Raina , Freescale Semiconductor Inc., 6501 William Cannon Drive West, Austin, TX 78735, USA
pp. 1-7

Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems (PDF)

Hsiu-Ming Chang , University of California, Santa Barbara, U.S.A.
Kwang-Ting Cheng , University of California, Santa Barbara, U.S.A.
pp. 1-10

Autonomic approaches for enhancing communication QoS in dense Wireless Sensor Networks with real time requirements (PDF)

A.R. Pinto , PGEAS - Universidade Federal de Santa Catarina - UFSC, Brazil
Carlos Montez , PGEAS - Universidade Federal de Santa Catarina - UFSC, Brazil
pp. 1-10

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability (PDF)

Stephan Eggersgluss , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1-10

AXIe®: Open architecture test system standard (PDF)

Al Czamara , Test Evolution, Inc., 102 South Street, Hopkinton, MA, 01742, USA
pp. 1

AXIe® 2.0 and MVP-C: Open ATE software standards (PDF)

Kenneth Spargo , Test Evolution, Inc. Hopkinton, MA. USA
pp. 1

A novel approach to improve test coverage of BSR cells (PDF)

Ankush Srivastava , Freescale Semiconductor, Inc. Noida, India
Ajay Prajapati , Freescale Semiconductor, Inc. Noida, India
Vinay Soni , Freescale Semiconductor, Inc. Noida, India
pp. 1

A MEMS based device interface board (PDF)

N. Kandalaft , Department of Electrical and Computer Engineering, University of Windsor, Canada
I. Basith , Department of Electrical and Computer Engineering, University of Windsor, Canada
R. Rashidzadeh , Department of Electrical and Computer Engineering, University of Windsor, Canada
pp. 1

Is test power reduction through X-filling good enough? (PDF)

F. Wu , LIRMM - Université Montpellier 2 / CNRS, France
L. Dilillo , LIRMM - Université Montpellier 2 / CNRS, France
A. Bosio , LIRMM - Université Montpellier 2 / CNRS, France
P. Girard , LIRMM - Université Montpellier 2 / CNRS, France
S. Pravossoudovitch , LIRMM - Université Montpellier 2 / CNRS, France
A. Virazel , LIRMM - Université Montpellier 2 / CNRS, France
M. Tehranipoor , University of Connecticut, Storrs, USA
K. Miyase , Kyushu Institute of Technology, Fukuoka, Japan
X. Wen , Kyushu Institute of Technology, Fukuoka, Japan
N. Ahmed , Texas Instruments, Dallas, USA
pp. 1

A tester architecture suitable for MEMS calibration and testing (PDF)

L. Ciganda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
P. Bernardi , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
D. Barbieri , SPEA Test Equipments, Italy
M. Straiotto , SPEA Test Equipments, Italy
L. Bonaria , SPEA Test Equipments, Italy
pp. 1

The AB-filling methodology for power-aware at-speed scan testing (PDF)

Tsung-Tang Chen , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei County, Taiwan, 25137, R.O.C.
Po-Han Wu , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei County, Taiwan, 25137, R.O.C.
Kung-Han Chen , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei County, Taiwan, 25137, R.O.C.
Jiann-Chyi Rau , Department of Electrical Engineering, Tamkang University, 151, Ying-Chuan Rd. Tamsui, Taipei County, Taiwan, 25137, R.O.C.
Shih-Ming Tzeng , Green Energy & Environment Research Laboratories, Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Chutung, Hsinchu, Taiwan 31040, R.O.C.
pp. 1

Scan chain securization though Open-Circuit Deadlocks (PDF)

Michele Portolan , Bell Labs Ireland, Dublin, Ireland
Bradford Van Treuren , Alcatel-Lucent Bell Labs, Murray Hill, NJ, USA
Suresh Goyal , Bell Labs Ireland, Dublin, Ireland
pp. 1

Using context based methods for test data compression (PDF)

Sara Karamati , Electrical and Computer Engineering Department, University of Tehran, Iran
Zainalabedin Navabi , Electrical and Computer Engineering Department, University of Tehran, Iran
pp. 1

A roaming memory test bench for detecting particle induced SEUs (PDF)

Jean-Marc Galliere , LIRMM - University of Montpellier / CNRS, France
Paolo Rech , LIRMM - University of Montpellier / CNRS, France
Patrick Girard , LIRMM - University of Montpellier / CNRS, France
Luigi Dilillo , LIRMM - University of Montpellier / CNRS, France
pp. 1

Detecting and diagnosing open defects (PDF)

Dat Tran , Freescale Semiconductor. Austin, TX, USA
LeRoy Winemberg , Freescale Semiconductor. Austin, TX, USA
Darrell Carder , Freescale Semiconductor. Austin, TX, USA
Xijiang Lin , Mentor Graphics Corp. Wilsonville, OR, USA
Joe LeBritton , Mentor Graphics Corp. Wilsonville, OR, USA
Bruce Swanson , Mentor Graphics Corp. Wilsonville, OR, USA
pp. 1

DFM aware bridge pair extraction for manufacturing test development (PDF)

Tammali Sarveswara , Texas Instruments Inc., USA
Vishal Khatri , BITS Pilani K. K. Birla Goa Campus, India
Gowrysankar Shanmugam , Texas Instruments Inc., USA
Mark Terry , Texas Instruments Inc., USA
pp. 1

Methodology for early and accurate test power estimation at RTL (PDF)

Abhay Singh , Purdue University, USA
Milan Shetty , Texas Instruments, India
Srivaths Ravi , Texas Instruments, India
Ravindra Nibandhe , Atrenta Inc, India
pp. 1

A practical scan re-use scheme for system test (PDF)

Kelly Lee , Texas Instruments Inc., USA
pp. 1

Mutation-based diagnostic test generation for hardware design error diagnosis (PDF)

Shujun Deng , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084 China
Kwang-Ting Cheng , Department of Electrical and Computer, Engineering, University of California, Santa Barbara, USA
Jinian Bian , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084 China
Zhiqiu Kong , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084 China
pp. 1

On generation of a universal path candidate set containing testable long paths (PDF)

Zijian He , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China
Tao Lv , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China
pp. 1

System reliability evaluation using concurrent multi-level simulation of structural faults (PDF)

Michael A. Kochte , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569, Germany
Christian G. Zoellin , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569, Germany
Rafal Baranowski , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569, Germany
Michael E. Imhof , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569, Germany
Nadereh Hatami , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
pp. 1

Case study of scan chain diagnosis and PFA on a low yield wafer (PDF)

Yu Huang , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Brady Benware , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Ting-Pu Tai , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Feng-Ming Kuo , Taiwan Semiconductor Manufacturing Company 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu, Taiwan 300-77, R. O. C.
Yuan-Shih Chen , Taiwan Semiconductor Manufacturing Company 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu, Taiwan 300-77, R. O. C.
pp. 1

Vendor-agnostic native compression engine (PDF)

Vance Threatt , Advanced Micro Devices, Inc., Austin, TX, USA
Atchyuth Gorti , Advanced Micro Devices, Inc., Austin, TX, USA
Jeff Rearick , Advanced Micro Devices, Inc., Fort Collins, CO; U.S.A.
Shaishav Parikh , Advanced Micro Devices, Inc., Austin, TX, USA
Anirudh Kadiyala , Advanced Micro Devices, Inc., Austin, TX, USA
Aditya Jagirdar , Advanced Micro Devices, Inc., Austin, TX, USA
Andy Halliday , Advanced Micro Devices, Inc., Austin, TX, USA
pp. 1

Parity prediction synthesis for nano-electronic gate designs (PDF)

D. A. Tran , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
A. Bosio , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
L. Dilillo , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Université Montpellier 2 / CNRS, 161, rue Ada - 34392 Cedex 5, France
H.-J. Wunderlich , Institut für Technische Informatik - Universität Stuttgart, Pfaffenwaldring 47 - D-70569, Germany
pp. 1

Multiple fault activation cycle tests for transistor stuck-open faults (PDF)

N. Devta-Prasanna , LSI Corp., Milpitas, CA, USA
A. Gunda , LSI Corp., Milpitas, CA, USA
S. M. Reddy , University of Iowa, Iowa City, USA
I. Pomeranz , Purdue University, West Lafayette, IN, USA
pp. 1
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