[Copyright notice] (PDF)
Steering committee and subcommittees (PDF)
ITC 2008 paper awards (PDF)
ITC 2009 most significant paper award (PDF)
ITC technical paper evaluation and selection process (PDF)
Invited address (PDF)
TTTC: Test Technology Technical Council (PDF)
2009 technical paper reviewers (PDF)
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs (PDF)
Test effectiveness evaluation through analysis of readily-available tester data (PDF)
Application of non-parametric statistics of the parametric response for defect diagnosis (PDF)
Testing bridges to nowhere - combining Boundary Scan and capacitive sensing (PDF)
Intel® IBIST, the full vision realized (PDF)
Fast extended test access via JTAG and FPGAs (PDF)
Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry (PDF)
Minimizing outlier delay test cost in the presence of systematic variability (PDF)
Accurate measurement of small delay defect coverage of test patterns (PDF)
Capture power reduction using clock gating aware test generation (PDF)
AutoRex: An automated post-silicon clock tuning tool (PDF)
Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family (PDF)
Data learning techniques and methodology for Fmax prediction (PDF)
Built-in EVM measurement for OFDM transceivers using all-digital DFT (PDF)
Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers (PDF)
Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations (PDF)
Fault diagnosis for embedded read-only memories (PDF)
A novel test flow for one-time-programming applications of NROM technology (PDF)
Voltage transient detection and induction for debug and test (PDF)
Cache-resident self-testing for I/O circuitry (PDF)
Compression-aware pseudo-functional testing (PDF)
Compression based on deterministic vector clustering of incompatible test cubes (PDF)
Augmenting board test coverage with new intel powered opens boundary scan instruction (PDF)
An outlier detection based approach for PCB testing (PDF)
SSC applied serial ATA signal generation and analysis by analog tester resources (PDF)
A robust method for identifying a deterministic jitter model in a total jitter distribution (PDF)
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing (PDF)
A timestamping method using reduced cost ADC hardware (PDF)
A novel architecture for on-chip path delay measurement (PDF)
Low cost test point insertion without using extra registers for high performance design (PDF)
Test economics for homogeneous manycore systems (PDF)
Physical defect modeling for fault insertion in system reliability test (PDF)
BIST scheme for RF VCOs allowing the self-correction of the cut (PDF)
A2DTest: A complete integrated solution for on-chip ADC self-test and analysis (PDF)
Thermal characterization of BIST, scan design and sequential test methodologies (PDF)
Cost-effective approach to improve EMI yield loss (PDF)
A development platform and electronic modules for automated test up to 20 Gbps (PDF)
Microprocessor system failures debug and fault isolation methodology (PDF)
Design for failure analysis inserting replacement-type observation points for LVP (PDF)
Feature based similarity search with application to speedpath analysis (PDF)
An ant colony optimization technique for abstraction-guided state justification (PDF)
Diagnostic test generation for transition faults using a stuck-at ATPG tool (PDF)
X-alignment techniques for improving the observability of response compactors (PDF)
An industrial case study for X-canceling MISR (PDF)
Test point insertion using functional flip-flops to drive control points (PDF)
Running scan test on three pins: yes we can! (PDF)
A novel array-based test methodology for local process variation monitoring (PDF)
Fast circuit topology based method to configure the scan chains in Illinois Scan architecture (PDF)
Structural test of power-only defects: ATPG or ad-hoc? (PDF)
Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line) (PDF)
Post-silicon validation: It's the unique fails that hurt you (PDF)
Structural test of power-only defects: ATPG or ad-hoc? (PDF)
Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line) (PDF)
Post-silicon validation: It's the unique fails that hurt you (PDF)
Tolerance of performance degrading faults for effective yield improvement (PDF)
The best of both worlds: Merging the benefits of Rack&Stack and universal ATE (PDF)
At-speed test on the QorIQTM P2020 platform (PDF)
Testing 3D chips containing through-silicon vias (PDF)
40 years of reliable computing at stanford CRC (PDF)
The ROAR project (1997–2002)— Looking Back (PDF)
The ARGOS project (PDF)
Test chip experiments at stanford CRC (PDF)
EDA for analog DFT? - designers must get on the bus (PDF)
Test challenges for 3D-SICs: All the old, most of the recent, and then some new! (PDF)
Implications of 3-D integrated circuits at board test position paper (PDF)
Power faults - What is our tolerance for defects? (PDF)
Physically aware DFT: Is it worth all the heavy lifting? (PDF)
Predictive solutions for test - The next DFT paradigm? (PDF)
Panel Synopsis - How (Un)affordable is true cost of test? (PDF)
Panel synopsis - How (Un)affordable is true cost of test? (PDF)
How (Un)affordable is the true cost of test? (PDF)
Eliminating product infant mortality failures using prognostic analysis (PDF)
Automatic diagnostic tool for Analog-Mixed Signal and RF load boards (PDF)
Scalable and efficient integrated test architecture (PDF)
Very-Low-Voltage testing of amorphous silicon TFT circuits (PDF)
Low power multi-chains encoding scheme for SoC in low-cost environment (PDF)
Power and thermal constrained test scheduling (PDF)
Power scan: DFT for power switches in VLSI designs (PDF)
IEEE P1687 IJTAG a presentation of current technology (PDF)
Test Mode Entry and Exit Methods for IEEE P1581 compliant devices (PDF)
A novel multisite testing techniques by using frequency synthesizer (PDF)
Design-for-secure-test for crypto cores (PDF)
Non-invasive RF built-in testing using on-chip temperature sensors (PDF)
NAND flash testing: A preliminary study on actual defects (PDF)
Built-in Self Test for Error Vector Magnitude measurement of RF transceiver (PDF)
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing (PDF)
Portable simulation/emulation stimulus on an industrial-strength SoC (PDF)
Test infrastructures evaluation at transaction level (PDF)
Trace signal selection for debugging electrical errors in post-silicon validation (PDF)
What is IEEE P1149.8.1 and why? (PDF)
Manufacturing data: Maximizing value using component-to-system analysis (PDF)
High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols (PDF)
Test access mechanism for multiple identical cores (PDF)