CSDL - 2009 International Test Conference - Table of Contents

2009 International Test Conference (2009)

Austin, TX USA

Nov. 1, 2009 to Nov. 6, 2009

ISBN: 978-1-4244-4868-5

TABLE OF CONTENTS

[Copyright notice] (PDF)

pp. ii

Steering committee and subcommittees (PDF)

pp. 2-3

ITC 2008 paper awards (PDF)

pp. 4

ITC 2009 most significant paper award (PDF)

pp. 5

ITC technical paper evaluation and selection process (PDF)

pp. 11

Invited address (PDF)

pp. 13

TTTC: Test Technology Technical Council (PDF)

pp. 14-16

2009 technical paper reviewers (PDF)

pp. 17-22

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study (PDF)

Sandeep Kumar Goel , LSI Corporation, 1621 Barber Lane, Milpitas CA 95035, USA

Narendra Devta-Prasanna , LSI Corporation, 1501 McCarthy Blvd, Milpitas CA 95035, USA

Mark Ward , LSI Corporation, 15220 NW Greenbrier Parkway, Beaverton OR 97006, USA

pp. 1-10

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs (PDF)

F. Hapke , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany

R. Krenz-Baath , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany

A. Glowatz , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany

J. Schloeffel , Mentor Graphics, Tempowerkring 1B, 21079 Hamburg, Germany

H. Hashempour , NXP Semiconductors, Prof. Holstlaan, HTC-46, 5656AA Eindhoven, The Netherlands

S. Eichenberger , NXP Semiconductors, Gerstweg 2, FD3, 6534AE Nijmengen, The Netherlands

C. Hora , NXP Semiconductors, Prof. Holstlaan, HTC-46, 5656AA Eindhoven, The Netherlands

D. Adolfsson , NXP Semiconductors, Prof. Holstlaan, HTC-46, 5656AA Eindhoven, The Netherlands

pp. 1-10

Test effectiveness evaluation through analysis of readily-available tester data (PDF)

Yen-Tzu Lin , Advanced Chip Testing Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA

R. D. Blanton , Advanced Chip Testing Laboratory, Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213, USA

pp. 1-10

Application of non-parametric statistics of the parametric response for defect diagnosis (PDF)

R. Gudavalli , Integrated Circuits Design and Test Laboratory, Electrical and Computer Engineering, Portland State University, Oregon 97201, USA

W.R. Daasch , Integrated Circuits Design and Test Laboratory, Electrical and Computer Engineering, Portland State University, Oregon 97201, USA

P. Nigh , IBM Corporation, Test Strategy and Development IBM Systems and Technology Group, 1000 River Road, MS-963G, Essex Junction, VT 05495, USA

D. Heaberlin , IBM Corporation, Test Strategy and Development IBM Systems and Technology Group, 1000 River Road, MS-963G, Essex Junction, VT 05495, USA

pp. 1-10

Testing bridges to nowhere - combining Boundary Scan and capacitive sensing (PDF)

Stephen Sunter , LogicVision, Malaysia

Kenneth P. Parker , Agilent Technologies, Malaysia

pp. 1-10

Intel^® IBIST, the full vision realized (PDF)

Jay Nejedlo , Intel Corporation, 2111 NE 25th Ave., Hillsboro, OR 97124, USA.

Rahul Khanna , Intel Corporation, 2111 NE 25th Ave., Hillsboro, OR 97124, USA.

pp. 1-11

Fast extended test access via JTAG and FPGAs (PDF)

Sergei Devadze , Testonica Lab O�, Tallinn, Estonia

Artur Jutman , Tallinn Univ. of Technology, Dept. of Comp. Engineering, Raja 15, 12618 Estonia

Igor Aleksejev , Testonica Lab O�, Tallinn, Estonia

Raimund Ubar , Tallinn Univ. of Technology, Dept. of Comp. Engineering, Raja 15, 12618 Estonia

pp. 1-7

Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry (PDF)

Philip B. Geiger , Dell Inc., Austin, TX, USA

Steve Butkovich , Cisco Systems Inc., San Jose, CA, USA

pp. 1-10

Minimizing outlier delay test cost in the presence of systematic variability (PDF)

Dragoljub Drmanac , University of California, Santa Barbara, USA

Brendon Bolin , University of California, Santa Barbara, USA

Li-C. Wang , University of California, Santa Barbara, USA

Magdy S. Abadir , Freescale Semiconductor, Inc., USA

pp. 1-10

Accurate measurement of small delay defect coverage of test patterns (PDF)

Narendra Devta-Prasanna , LSI Corporation, 1501 McCarthy Blvd., Milpitas CA 95035, USA

Sandeep Kumar Goel , LSI Corporation, 1621 Barber Lane, Milpitas CA 95035, USA

Arun Gunda , LSI Corporation, 1501 McCarthy Blvd., Milpitas CA 95035, USA

Mark Ward , LSI Corporation, 15220 NW Greenbrier Parkway, Beaverton OR 97006, USA

Prabhakaran Krishnamurthy , LSI Corporation, 1501 McCarthy Blvd., Milpitas CA 95035, USA

pp. 1-10

Capture power reduction using clock gating aware test generation (PDF)

Krishna Chakravadhanula , Front-End Design Group, Cadence Design Systems, USA

Vivek Chickermane , Front-End Design Group, Cadence Design Systems, USA

Brion Keller , Front-End Design Group, Cadence Design Systems, USA

Patrick Gallagher , Front-End Design Group, Cadence Design Systems, USA

Prashant Narang , Front-End Design Group, Cadence Design Systems, USA

pp. 1-9

AutoRex: An automated post-silicon clock tuning tool (PDF)

D. Tadesse , Brown University, Division of Engineering, Providence, RI 02912, USA

J. Grodstein , Intel Corporation, Hudson, MA 01749, USA

R. I. Bahar , Brown University, Division of Engineering, Providence, RI 02912, USA

pp. 1-10

Using transition test to understand timing behavior of logic circuits on UltraSPARC^TM T2 family (PDF)

Liang-Chi Chen , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

Paul Dickinson , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

Peter Dahlgren , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

Scott Davidson , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

Olivier Caty , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

Kevin Wu , Sun Microsystems, 324 N. Mary Ave, Sunnyvale, CA 94085, USA

pp. 1-10

Data learning techniques and methodology for Fmax prediction (PDF)

Janine Chen , Department of ECE, UC-Santa Barbara, USA

Li-C. Wang , Department of ECE, UC-Santa Barbara, USA

Po-Hsien Chang , Department of ECE, UC-Santa Barbara, USA

Jing Zeng , Advanced Micro Devices, Inc., USA

Stanley Yu , Advanced Micro Devices, Inc., USA

Michael Mateja , Advanced Micro Devices, Inc., USA

pp. 1-10

Built-in EVM measurement for OFDM transceivers using all-digital DFT (PDF)

Ender Yilmaz , Arizona State University, Electrical Engineering Department, USA

Afsaneh Nassery , Arizona State University, Electrical Engineering Department, USA

Sule Ozev , Arizona State University, Electrical Engineering Department, USA

Erkan Acar , Duke University Durham, NC, USA

pp. 1-10

Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers (PDF)

Bobby Lai , Wireless Terminal Business Unit of Texas Instruments Incorporated, 12500 TI Blvd, Dallas, 75243, USA

Chris Rivera , Wireless Terminal Business Unit of Texas Instruments Incorporated, 12500 TI Blvd, Dallas, 75243, USA

Khurram Waheed , Wireless Terminal Business Unit of Texas Instruments Incorporated, 12500 TI Blvd, Dallas, 75243, USA

pp. 1-7

Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations (PDF)

Shreyas Sen , Georgia Institute of Technology, Atlanta, USA

Shyam Devarakond , Georgia Institute of Technology, Atlanta, USA

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, USA

pp. 1-10

Fault diagnosis for embedded read-only memories (PDF)

N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

A. Pogiel , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

J. Tyszer , Pozna� University of Technology, 60-965, Poland

pp. 1-10

A novel test flow for one-time-programming applications of NROM technology (PDF)

Ching-Yu Chin , Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

Yao-Te Tsou , Macronix International Co., Ltd., Hsinchu, Taiwan

Chi-Min Chang , Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

Mango C.-T. Chao , Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan

pp. 1-9

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design (PDF)

Hsiang-Huang Wu , Department of Electrical & Computer Engineering, University of Maryland, College Park, USA

Jih-Nung Lee , Realtek Semiconductor Corp., Hsinchu, Taiwan

Ming-Cheng Chiang , Realtek Semiconductor Corp., Hsinchu, Taiwan

Po-Wei Liu , Realtek Semiconductor Corp., Hsinchu, Taiwan

Chi-Feng Wu , Realtek Semiconductor Corp., Hsinchu, Taiwan

pp. 1-10

On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC) (PDF)

Franco Stellari , IBM T.J. Watson Research Center, Yorktown Height, NY, USA

Peilin Song , IBM T.J. Watson Research Center, Yorktown Height, NY, USA

John Sylvestri , IBM System and Technology Group, Hopewell Junction, NY, USA

Darrell Miles , IBM System and Technology Group, Hopewell Junction, NY, USA

Orazio Forlenza , IBM System and Technology Group, Hopewell Junction, NY, USA

Donato Forlenza , IBM System and Technology Group, Hopewell Junction, NY, USA

pp. 1-10

Voltage transient detection and induction for debug and test (PDF)

Rex Petersen , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

Pankaj Pant , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

Pablo Lopez , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

Aaron Barton , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

Jim Ignowski , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

Doug Josephson , Intel Corporation, Hudson, MA and Fort Collins, CO, USA

pp. 1-10

Cache-resident self-testing for I/O circuitry (PDF)

Sankar Gurumurthy , Advanced Micro Devices, Inc.: Austin, TX, USA

Darren Bertanzetti , Advanced Micro Devices, Inc.: Fort Collins, CO, USA

Peter Jakobsen , Advanced Micro Devices, Inc.: Fort Collins, CO, USA

Jeff Rearick , Advanced Micro Devices, Inc.: Fort Collins, CO, USA

pp. 1-8

Compression-aware pseudo-functional testing (PDF)

Feng Yuan , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

pp. 1-10

Compression based on deterministic vector clustering of incompatible test cubes (PDF)

G. Mrugalski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

N. Mukherjee , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

J. Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA

D. Czysz , Pozna� University of Technology, 60-965, Poland

J. Tyszer , Pozna� University of Technology, 60-965, Poland

pp. 1-10

On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment (PDF)

Xiao Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

pp. 1-10

An economical, precise and limited access In-Circuit Test method for pulse-width modulation (PWM) circuits (PDF)

Albert Yeh , Test Research Inc., Taipei, Taiwan

Jesse Chou , Test Research Inc., Taipei, Taiwan

Max Lin , Test Research Inc., Taipei, Taiwan

pp. 1-9

Augmenting board test coverage with new intel powered opens boundary scan instruction (PDF)

Chwee Liong Tee , Intel� Corporation, Kulim, Malaysia

Tzyy Haw Tan , Intel� Corporation, Kulim, Malaysia

Chin Chuan Ng , Intel� Corporation, Kulim, Malaysia

pp. 1-10

An outlier detection based approach for PCB testing (PDF)

Xin He , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, 80523, USA

Yashwant Malaiya , Department of Computer Science, Colorado State University, Fort Collins, 80523, USA

Anura P. Jayasumana , Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, 80523, USA

Kenneth P. Parker , Agilent Technologies, Loveland, CO 80537, USA

Stephen Hird , Agilent Technologies, Loveland, CO 80537, USA

pp. 1-10

SSC applied serial ATA signal generation and analysis by analog tester resources (PDF)

Hideo Okawara , Verigy Japan K.K. Tokyo, Japan

pp. 1-9

A robust method for identifying a deterministic jitter model in a total jitter distribution (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan

Kiyotaka Ichiyama , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan

Harry X. Hou , Advantest America, Inc., Santa Clara, CA, USA

Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan

pp. 1-10

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing (PDF)

T. Fujibe , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

M. Suda , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

K. Yamamoto , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

Y. Nagata , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

K. Fujita , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

D. Watanabe , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

T. Okayasu , ADVANTEST Corporation, 336-1, Ohwa, Meiwa-machi, Ora-gun, Gunma 370-0718, Japan

pp. 1-10

A timestamping method using reduced cost ADC hardware (PDF)

Timothy D. Lyons , Teradyne, Inc. North Reading, MA, USA

pp. 1-8

A novel architecture for on-chip path delay measurement (PDF)

Xiaoxiao Wang , ECE Dept, University of Connecticut, USA

Mohammad Tehranipoor , ECE Dept, University of Connecticut, USA

Ramyanshu Datta , Texas Instruments, USA

pp. 1-10

Low cost test point insertion without using extra registers for high performance design (PDF)

Haoxing Ren , IBM Corporation, USA

Mary Kusko , IBM Corporation, USA

Victor Kravets , IBM Corporation, USA

Rona Yaari , IBM Corporation, USA

pp. 1-8

Test economics for homogeneous manycore systems (PDF)

Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China

pp. 1-10

Physical defect modeling for fault insertion in system reliability test (PDF)

Zhaobo Zhang , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA

Zhanglei Wang , Cisco Systems, Inc., San Jose, CA 95134, USA

Xinli Gu , Cisco Systems, Inc., San Jose, CA 95134, USA

Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA

pp. 1-10

BIST scheme for RF VCOs allowing the self-correction of the cut (PDF)

L. Testa , IMS Lab - Bordeaux - France

H. Lapuyade , IMS Lab - Bordeaux - France

Y. Deval , IMS Lab - Bordeaux - France

O. Mazouffre , IMS Lab - Bordeaux - France

J.L. Carbonero , STMicroelectronics - Crolles - France

J.B. Begueret , IMS Lab - Bordeaux - France

pp. 1-10

A2DTest: A complete integrated solution for on-chip ADC self-test and analysis (PDF)

Brendan Mullane , Department of Electronic and Computer Engineering, University of Limerick, Ireland

Vincent O'Brien , Department of Electronic and Computer Engineering, University of Limerick, Ireland

Ciaran MacNamee , Department of Electronic and Computer Engineering, University of Limerick, Ireland

Thomas Fleischmann , Department of Electronic and Computer Engineering, University of Limerick, Ireland

pp. 1-10

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing (PDF)

Masashi Shimanouchi , Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA

Mike Peng Li , Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA

Daniel Chow , Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA

pp. 1-8

Thermal characterization of BIST, scan design and sequential test methodologies (PDF)

Muzaffer O. Simsir , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA

Niraj K. Jha , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA

pp. 1-9

Cost-effective approach to improve EMI yield loss (PDF)

Hsuan-Chung Ko , King Yuan Electronics Co. Ltd., Taiwan

Deng-Yao Chang , King Yuan Electronics Co. Ltd., Taiwan

Cheng-Nan Hu , Oriental Institute of Technology, Taiwan

pp. 1-8

A development platform and electronic modules for automated test up to 20 Gbps (PDF)

D.C. Keezer , Georgia Institute of Technology, Atlanta, USA

C. Gray , Georgia Institute of Technology, Atlanta, USA

A. Majid , Georgia Institute of Technology, Atlanta, USA

D. Minier , IBM, Bromont, Canada

P. Ducharme , IBM, Bromont, Canada

pp. 1-11

Microprocessor system failures debug and fault isolation methodology (PDF)

M. Enamul Amyeen , Intel Corporation, Hillsboro, OR, USA

Srikanth Venkataraman , Intel Corporation, Hillsboro, OR, USA

Mun Wai Mak , Intel Corporation, Hillsboro, OR, USA

pp. 1-10

Design for failure analysis inserting replacement-type observation points for LVP (PDF)

Junpei Nonaka , Test and Analysis Engineering Division, NEC ELECTRONICS CORPORATION, 1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan

Toshio Ishiyama , Test and Analysis Engineering Division, NEC ELECTRONICS CORPORATION, 1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan

Kazuki Shigeta , Test and Analysis Engineering Division, NEC ELECTRONICS CORPORATION, 1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan

pp. 1-10

Feature based similarity search with application to speedpath analysis (PDF)

Nicholas Callegari , University of California - Santa Barbara, USA

Li-C. Wang , University of California - Santa Barbara, USA

Pouria Bastani , Intel Corporation, USA

pp. 1-10

Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning (PDF)

Chia-Ling Chang , Dept. of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan 300

Charles H.-P. Wen , Dept. of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan 300

Jayanta Bhadra , Freescale Semiconductor Inc., Austin, TX 78729, USA

pp. 1-8

An ant colony optimization technique for abstraction-guided state justification (PDF)

Min Li , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

pp. 1-10

Diagnostic test generation for transition faults using a stuck-at ATPG tool (PDF)

Yoshinobu Higami , Graduate School of Science and Engineering, Ehime University, Japan

Yosuke Kurose , Graduate School of Science and Engineering, Ehime University, Japan

Satoshi Ohno , Graduate School of Science and Engineering, Ehime University, Japan

Hironori Yamaoka , Graduate School of Science and Engineering, Ehime University, Japan

Hiroshi Takahashi , Graduate School of Science and Engineering, Ehime University, Japan

Yoshihiro Shimizu , Semiconductor Technology Academic Research Center, Japan

Takashi Aikyo , Semiconductor Technology Academic Research Center, Japan

Yuzo Takamatsu , Graduate School of Science and Engineering, Ehime University, Japan

pp. 1-9

X-alignment techniques for improving the observability of response compactors (PDF)

Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University, Kuwait

Sobeeh Almukhaizim , Computer Engineering Department, Kuwait University, Kuwait

pp. 1-10

An industrial case study for X-canceling MISR (PDF)

Joon-Sung Yang , Computer Engineering Research Center, University of Texas, Austin, 78712, USA

Nur A. Touba , Computer Engineering Research Center, University of Texas, Austin, 78712, USA

Shih-Yu Yang , Intel Corporation, Portland, OR 97124, USA

T.M. Mak , Intel Corporation, Portland, OR 97124, USA

pp. 1-10

Test point insertion using functional flip-flops to drive control points (PDF)

Joon-Sung Yang , Computer Engineering Research Center, Dept. of Electrical and Computer Engineering, University of Texas, Austin, 78712, USA

Benoit Nadeau-Dostie , Logic Vision, Inc., 25 Metro Drive, Third Floor, San Jose, CA 95110, USA

Nur A. Touba , Computer Engineering Research Center, Dept. of Electrical and Computer Engineering, University of Texas, Austin, 78712, USA

pp. 1-10

Running scan test on three pins: yes we can! (PDF)

Jocelyn Moreau , STMicroelectronics, Imaging division, 12, rue Jules Horowitz - BP 217. F-38019 Grenoble Cedex, France

Thomas Droniou , STMicroelectronics, Imaging division, 12, rue Jules Horowitz - BP 217. F-38019 Grenoble Cedex, France

Philippe Lebourg , STMicroelectronics, Imaging division, 12, rue Jules Horowitz - BP 217. F-38019 Grenoble Cedex, France

Paul Armagnat , STMicroelectronics, Imaging division, 12, rue Jules Horowitz - BP 217. F-38019 Grenoble Cedex, France

pp. 1-10

A novel array-based test methodology for local process variation monitoring (PDF)

Tseng-Chin Luo , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Mango C.-T. Chao , Dept. of Electronics Engineering National Chiao Tung Univ., Hsinchu, Taiwan

Michael S.-Y. Wu , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Kuo-Tsai Li , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Chin. C. Hsia , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Huan-Chi Tseng , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Chuen-Uan Huang , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Yuan-Yao Chang , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Samuel C. Pan , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

Konrad K.-L. Young , Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan

pp. 1-9

Fast circuit topology based method to configure the scan chains in Illinois Scan architecture (PDF)

Swapneel Donglikar , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

Mainak Banga , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

Maheshwar Chandrasekar , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA

pp. 1-10

Structural test of power-only defects: ATPG or ad-hoc? (PDF)

Baosheng Wang , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Grady Giles , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Jayalakshmi Rajaraman , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Kanwaldeep Sobti , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Derrick Losli , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Dwight Elvey , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Jeff Fitzgerald , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Ron Walther , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

Jeff Rearick , Advanced Micro Devices, Inc., 1AMD Pl., Sunnyvale, CA 94086, USA

pp. 1

Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line) (PDF)

Fassely Doumbia , AIRBUS France, 316 route de Bayonne, 31060 Toulouse Cedex 09, France

Odile Laurent , AIRBUS France, 316 route de Bayonne, 31060 Toulouse Cedex 09, France

Didier Atger , AIRBUS France, 316 route de Bayonne, 31060 Toulouse Cedex 09, France

Chantal Robach , LCIS - Grenoble INP, 50 rue Barth�l�my de Laffemas, 26902 Valence Cedex 09, France

pp. 1-9

Post-silicon validation: It's the unique fails that hurt you (PDF)

P. K. Ahuja , Sun Microsystems, USA