The Community for Technology Leaders
2008 IEEE International Test Conference (2008)
Santa Clara, CA USA
Oct. 28, 2008 to Oct. 30, 2008
ISSN: 1089-3539
ISBN: 978-1-4244-2402-3
TABLE OF CONTENTS

Managing Test in the End-to-End, Mega Supply Chain (PDF)

Mike Lydon , Vice President, Technology and Quality, Global Supply Chain Management, Cisco
pp. 12

Computing at the Crossroads (And What Does it Mean to Verification and Test?) (PDF)

Jan N. Rabaey , Donald O. Pederson Distinguished Professor, University of California at Berkeley
pp. 13

Having FUN with Analog Test (PDF)

Robert A. Pease , Staff Scientist, National Semiconductor
pp. 14

A Study of Outlier Analysis Techniques for Delay Testing (PDF)

Sean H. Wu , Department of ECE, UC-Santa Barbara
Dragoljub Drmanac , Department of ECE, UC-Santa Barbara
Li-C. Wang , Department of ECE, UC-Santa Barbara
pp. 1-10

Production Multivariate Outlier Detection Using Principal Components (PDF)

Peter M. O'Neill , Avago Technologies, Inc. Fort Collins, CO, USA
pp. 1-10

Unraveling Variability for Process/Product Improvement (PDF)

Anne Gattiker , IBM Research Division, Austin Research Lab, 11501 Burnet Road, Austin TX 78758, USA. gattiker@us.ibm.com
pp. 1-9

The Test Features of the Quad-Core AMD Opteron- Microprocessor (PDF)

Tim Wood , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Grady Giles , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Chris Kiszely , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Martin Schuessler , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Daniela Toneva , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Joel Irby , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
Michael Mateja , Advanced Micro Devices, 7171 Southwest Pkwy, Austin, TX. 78735
pp. 1-10

DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor (PDF)

Ishwar Parulkar , Sun Microsystems, Inc., Santa Clara, CA 95054
Sriram Anandakumar , Sun Microsystems, Inc., Santa Clara, CA 95054
Gaurav Agarwal , Sun Microsystems, Inc., Santa Clara, CA 95054
Gordon Liu , Sun Microsystems, Inc., Santa Clara, CA 95054
Krishna Rajan , Sun Microsystems, Inc., Santa Clara, CA 95054
Frank Chiu , Sun Microsystems, Inc., Santa Clara, CA 95054
Rajesh Pendurkar , Sun Microsystems; RMI Corporation, Cupertino, CA 95014
pp. 1-10

Test Access Mechanism for Multiple Identical Cores (PDF)

Grady Giles , Advanced Micro Devices Austin, USA and Sunnyvale, USA
Jing Wang , Advanced Micro Devices Austin, USA and Sunnyvale, USA
Anuja Sehgal , Advanced Micro Devices Austin, USA and Sunnyvale, USA
Kedarnath J. Balakrishnan , Advanced Micro Devices Austin, USA and Sunnyvale, USA
James Wingfield , Advanced Micro Devices Austin, USA and Sunnyvale, USA
pp. 1-10

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST (PDF)

Nilanjan Mukherjee , Mentor Graphics Corporation, 8005 S. W. Boeckman Road, Wilsonville, OR 97070, USA
Artur Pogiel , Pozna¿ University of Technology, ul. Piotrowo 3a, 60-965 Pozna¿, Poland
Janusz Rajski , Mentor Graphics Corporation, 8005 S. W. Boeckman Road, Wilsonville, OR 97070, USA
Jerzy Tyszer , Pozna¿ University of Technology, ul. Piotrowo 3a, 60-965 Pozna¿, Poland
pp. 1-10

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs (PDF)

A. Ney , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: ney@lirmm.fr
A. Bosio , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: bosio@lirmm.fr
L. Dilillo , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: dilillo@lirmm.fr
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: girard@lirmm.fr
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: pravo@lirmm.fr
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: virazel@lirmm.fr
M. Bastian , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France. Email: magali.bastian@infineon.com
pp. 1-10

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation (PDF)

W. Kong , IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533. weikong@us.ibm.com
P. C. Parries , IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533
G. Wang , IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533
S. S. Iyer , IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533
pp. 1-7

External Loopback Testing Experiences with High Speed Serial Interfaces (PDF)

Anne Meixner , Intel Corporation
Akira Kakizawa , Intel Corporation
Benoit Provost , Intel Corporation
Serge Bedwani , Intel Corporation
pp. 1-10

Low cost testing of multi-GBit device pins with ATE assisted loopback instrument (PDF)

William A Fritzsche , Credence Systems Corporation, 1421 California Circle, Milpitas, CA 95035, USA. william_fritzsche@credence.com
Asim E. Haque , Credence Systems Corporation, 1421 California Circle, Milpitas, CA 95035, USA. asim_haque@credence.com
pp. 1-8

Efficient High-Speed Interface Verification and Fault Analysis (PDF)

Thomas Nirmaier , Infineon / Qimonda AG, Am Campeon 9, 81609, Munich, Germany. e-mail: thomas.nirmaier@infineon.com
Jose Torres Zaguirre , Infineon / Qimonda AG, Am Campeon 9, 81609, Munich, Germany
Eric Liau Chee Hong , Infineon / Qimonda AG, Am Campeon 9, 81609, Munich, Germany
Wolfgang Spirkl , Infineon / Qimonda AG, Am Campeon 9, 81609, Munich, Germany
Armin Rettenberger , Infineon / Qimonda AG, Am Campeon 9, 81609, Munich, Germany
Doris Schmitt-Landsiedel , Technical University Munich, Theresienstr. 90, 80290, Munich, Germany
pp. 1-9

Implementation Update: Logic Mapping On SPARC- Microprocessors (PDF)

Anjali Vij , Texas Instruments Inc. anjali@ti.com
Richard Ratliff , Texas Instruments Inc. rratliff@ti.com
pp. 1-10

Failing Frequency Signature Analysis (PDF)

Jaekwang Lee , Center for Reliable Computing, Stanford University, Stanford, CA USA
Edward J. McCluskey , Center for Reliable Computing, Stanford University, Stanford, CA USA
pp. 1-8

A Cost Analysis Framework for Multi-core Systems with Spares (PDF)

Saeed Shamshiri , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. saeedshamshiri@ece.ucsb.edu
Peter Lisherness , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. peter@ece.ucsb.edu
Sung-Jui Pan , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. srpan@ece.ucsb.edu
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. timcheng@ece.ucsb.edu
pp. 1-8

Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects (PDF)

Adit D. Singh , Electrical & Computer Engineering, Auburn University, AL 36849
pp. 1-8

On-chip Programmable Capture for Accurate Path Delay Test and Characterization (PDF)

Rajeshwary Tayade , University of Texas, Austin. rajeshwary@cerc.utexas.edu
Jacob A. Abraham , University of Texas, Austin. jaa@cerc.utexas.edu
pp. 1-10

An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements (PDF)

Kelageri Nagaraj , Department of Electrical & Computer Engineering, University of Massachusetts, Amherst, USA. Email: nagaraj@ecs.umass.edu
Sandip Kundu , Department of Electrical & Computer Engineering, University of Massachusetts, Amherst, USA. Email: kundu@ecs.umass.edu
pp. 1-8

CONCAT: CONflict Driven Learning in ATPG for Industrial designs (PDF)

Surendra Bommu , Intel Corporation, Santa Clara, CA 95054. surendra.k.bommu@intel.com
Kameshwar Chandrasekar , Intel Corporation, Santa Clara, CA 95054. kameshwar.chandrasekar@intel.com
Rahul Kundu , Intel Corporation, Santa Clara, CA 95054. rahul.kundu@intel.com
Sanjay Sengupta , Intel Corporation, Santa Clara, CA 95054. sanjay.sengupta@intel.com
pp. 1-10

SAT-based State Justification with Adaptive Mining of Invariants (PDF)

Weixin Wu , Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA. wuw@vt.edu
Michael S. Hsiao , Department of Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA. mhsiao@vt.edu
pp. 1-10

RTL Error Diagnosis Using a Word-Level SAT-Solver (PDF)

Saeed Mirzaeian , Department of Electrical and Computer Engineering, University of California, Santa Barbara. saeed@ece.ucsb.edu
Feijun Zheng , Department of Electrical and Computer Engineering, Zhejiang University, China. zhengfj@ece.ucsb.edu
K.-T. Tim Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara. timcheng@ece.ucsb.edu
pp. 1-8

Embedded Power Delivery Decoupling in Small Form Factor Test Sockets (PDF)

Omer Vikinski , omer.vikinski@intel.com
Shaul Lupo , shaul.lupo@intel.com
Gregory Sizikov , gregory.sizikov@intel.com
Chee Yee Chung , chee.yee.chung@intel.com
pp. 1-8

Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications (PDF)

Thomas P. Warwick , Evaluation and Product Engineering, Inc.
Gustavo Rivera , Qualcomm Corporation
David Waite , Qualcomm Corporation
James Russell , R&D Circuits, Inc.
Jeffrey Smith , Qualcomm Corporation
pp. 1-10

Wafer-Level Characterization of Probecards using NAC Probing (PDF)

Gyu-Yeol Kim , Sungkyunkwan University, Department of ECE; Samsung Electronics, Memory Division, Wafer Test Technology Team. gyul.kim@samsung.com, Phone: 82-31-208-6781, Fax: 82-31-208-4989
Eon-Jo Byun , Samsung Electronics, Memory Division, Wafer Test Technology Team
Ki-Sang Kang , Samsung Electronics, Memory Division, Wafer Test Technology Team
Young-Hyun Jun , Samsung Electronics, Memory Division, DRAM Design Team
Bai-Sun Kong , Sungkyunkwan University, Department of ECE
pp. 1-9

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs (PDF)

Vivek Chickermane , Front-End Design Group, Cadence Design Systems, USA. vivekc@cadence.com
Patrick Gallagher , Front-End Design Group, Cadence Design Systems, USA. patrickg@cadence.com
James Sage , Front-End Design Group, Cadence Design Systems, USA. sagejm@cadence.com
Paul Yuan , Front-End Design Group, Cadence Design Systems, USA. paulyuan@cadence.com
Krishna Chakravadhanula , Front-End Design Group, Cadence Design Systems, USA. ckrishna@cadence.com
pp. 1-10

Peak Power Reduction Through Dynamic Partitioning of Scan Chains (PDF)

Sobeeh Almukhaizim , Computer Engineering Department, Kuwait University. sobeeh@eng.kuniv.edu.kw
Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University. ozgur@sci.kuniv.edu.kw
pp. 1-10

Time-dependent Behaviour of Full Open Defects in Interconnect Lines (Abstract)

R. Rodriguez-Montanes , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, SPAIN
D. Arumi , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, SPAIN
J. Figueras , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, SPAIN
S. Eichenberger , NXP Semiconductors, THE NETHERLANDS. stefan.eichenberger@nxp.com
C. Hora , NXP Semiconductors, THE NETHERLANDS. camelia.hora@nxp.com
B. Kruseman , NXP Semiconductors, THE NETHERLANDS. bram.kruseman@nxp.com
pp. 1-10

Statistical Yield Modeling for Sub-wavelength Lithography (PDF)

Aswin Sreedhar , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst. Email: asreedha@ecs.umass.edu
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts at Amherst. Email: kundu@ecs.umass.edu
pp. 1-8

Detection of Internal Stuck-open Faults in Scan Chains (PDF)

F. Yang , University of Iowa, Iowa City, Iowa City, IA
S. Chakravarty , LSI Corporation, Milpitas, CA
N. Devta-Prasanna , LSI Corporation, Milpitas, CA
S.M. Reddy , University of Iowa, Iowa City, Iowa City, IA
I. Pomeranz , Purdue University, West Lafayette, IN
pp. 1-10

Engineering Test Coverage on Complex Sockets (PDF)

Myron J. Schneider , Agilent Technologies, Loveland, CO. Myron_Schneider@Agilent.com
Ayub Shafi , Advanced Micro Devices, Austin, TX. Ayub.Shafi@AMD.com
pp. 1-9

Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application (PDF)

Dave Dubberke , Intel® Corporation, 5200 NE Elam Young Parkway, Hillsboro, OR 97124. dave.f.dubberke@intel.com
JJ Grealish , Intel® Corporation, 5200 NE Elam Young Parkway, Hillsboro, OR 97124. james.grealish@intel.com
Bill Van Dick , Intel® Corporation, 5200 NE Elam Young Parkway, Hillsboro, OR 97124. bill.i.van.dick@intel.com
pp. 1-9

Augmenting Boundary-Scan Tests for Enhanced Defect Coverage (PDF)

Dayton Norrgard , Agilent Technologies, Loveland, Colorado. dayton_norrgard@agilent.com
Kenneth P. Parker , Agilent Technologies, Loveland, Colorado. kenneth_parker@agilent.com
pp. 1-8

Low Energy On-Line SBST of Embedded Processors (PDF)

A. Merentitis , Department of Informatics & Telecommunications, University of Athens, Greece. amer@di.uoa.gr
N. Kranitis , Department of Informatics & Telecommunications, University of Athens, Greece. nkran@di.uoa.gr
A. Paschalis , Department of Informatics & Telecommunications, University of Athens, Greece. paschali@di.uoa.gr
D. Gizopoulos , Department of Informatics, University of Piraeus, Greece. dgizop@unipi.gr
pp. 1-10

On-line Failure Detection in Memory Order Buffers (PDF)

J. Carretero , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya. javierx.carretero.casado@intel.com
X. Vera , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya. xavier.vera@intel.com
P. Chaparro , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya. pedro.chaparro.monferrer@intel.com
J. Abella , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya. jaume.abella@intel.com
pp. 1-10

VAST: Virtualization-Assisted Concurrent Autonomous Self-Test (PDF)

Hiroaki Inoue , Departments of Electrical Engineering and Computer Science, Stanford University; System IP Core Research Laboratories, NEC Corporation
Yanjing Li , Departments of Electrical Engineering and Computer Science, Stanford University
Subhasish Mitra , Departments of Electrical Engineering and Computer Science, Stanford University
pp. 1-10

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing (PDF)

Meng-Fan Wu , Graduate Institute of Electronics Engineering, Dept. of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Jiun-Lang Huang , Graduate Institute of Electronics Engineering, Dept. of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Xiaoqing Wen , Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan
Kohei Miyase , Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan
pp. 1-10

Low Power Scan Shift and Capture in the EDT Environment (PDF)

D. Czysz , Pozna¿ University of Technology, ul. Piotrowo 3a, 60-965 Pozna¿, Poland
M. Kassab , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
X. Lin , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
G. Mrugalski , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
J. Tyszer , Pozna¿ University of Technology, ul. Piotrowo 3a, 60-965 Pozna¿, Poland
pp. 1-10

Frequency and Power Correlation between At-Speed Scan and Functional Tests (PDF)

Shlomi Sde-Paz , Freescale Semiconductor Israel Ltd., 1 Shenkar St., Herzylia, Israel
Eyal Salomon , Freescale Semiconductor Israel Ltd., 1 Shenkar St., Herzylia, Israel
pp. 1-9

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects (PDF)

Fei Wang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; Graduate University of Chinese Academy of Sciences, Beijing, China. wang_fei@ict.ac.cn
Hu Yu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China. huyu@ict.ac.cn
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China. lihuawei@ict.ac.cn
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China. lxw@ict.ac.cn
Jing Ye , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; Graduate University of Chinese Academy of Sciences, Beijing, China.
Huang Yu , Mentor Graphics Corporation, 300 Nickerson Rd., Marlborough, MA, 01752, USA. yu_huang@mentor.com
pp. 1-10

Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained (PDF)

Pouria Bastani , Department of ECE, UC-Santa Barbara
Nick Callegari , Department of ECE, UC-Santa Barbara
Li-C. Wang , Department of ECE, UC-Santa Barbara
Magdy S. Abadir , Freescale Semiconductor, Inc.
pp. 1-10

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data (PDF)

Huaxing Tang , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. huaxing_tang@mentor.com
Manish Sharma , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. manish_sharma@mentor.com
Lei Ling , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA.
David Abercrombie , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA.
Lincoln Lee , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA.
Martin Keim , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. martin_keim@mentor.com
Brady Benware , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. brady_benware@mentor.com
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. wu-tung_cheng@mentor.com
Ting-Pu Tai , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA. ting-pu_tai@mentor.com
Yi-Jung Chang , UMC, No. 3, Li-Hsin 2nd Road, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C., I_Y_Chang@umc.com
Reinhart Lin , UMC, No. 3, Li-Hsin 2nd Road, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C., Reinhart_Lin@umc.com
Albert Man , AMD, Inc., 1CV Commerce Valley Drive E., Markham, Ont Canada, L3T 7N6. albert.man@amd.com
pp. 1-9

Solder Bead on High Density Interconnect Printed Circuit Board (PDF)

Brandon Chu , Intel Corporation, 5200 NE Elam Young Parkway, Hillsboro, OR 97124. brandon.chu@intel.com
pp. 1-5

Finding Power/Ground Defects on Connectors - Case Study (PDF)

Steve Hird , Agilent Technologies, Loveland, CO
Reggie Weng , Agilent Technologies, Taiwan
pp. 1-4

Architecture for Testing Multi-Voltage Domain SOC (PDF)

Laurent Souef , ST NXP Wireless Semiconductors Sophia, 505 route des Lucioles, 06560 Valbonne, France. laurent.souef@nxp.com
Christophe Eychenne , ST NXP Wireless Semiconductors Sophia, 505 route des Lucioles, 06560 Valbonne, France. christophe.eychenne@nxp.com
Emmanuel Alie , ST NXP Wireless Semiconductors Sophia, 505 route des Lucioles, 06560 Valbonne, France. emmanuel.alie@nxp.com
pp. 1-10

Integration of Hardware Assertions in Systems-on-Chip (PDF)

Jeroen Geuzebroek , NXP Semiconductors, Corporate Innovation & Technology / Research, High Tech Campus 37, 5656 AE Eindhoven, The Netherlands. jeroen.geuzebroek@nxp.com
Bart Vermeulen , NXP Semiconductors, Corporate Innovation & Technology / Research, High Tech Campus 37, 5656 AE Eindhoven, The Netherlands. bart.vermeulen@nxp.com
pp. 1-10

Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs (PDF)

Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: henryko@grads.ece.mcmaster.ca
Adam B. Kinsman , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: kinsmaab@mcmaster.ca
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: nicola@ece.mcmaster.ca
pp. 1-10

An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis (PDF)

Xiaochun Yu , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, U.S.A., xyu1@ece.cmu.edu
R. D. Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213, U.S.A., blanton@ece.cmu.edu
pp. 1-9

Detection and Diagnosis of Static Scan Cell Internal Defect (PDF)

Ruifeng Guo , Mentor Graphics Corp. Wilsonville, OR 97070. ruifeng_guo@mentor.com
Liyang Lai , Mentor Graphics Corp. Wilsonville, OR 97070. liyang_lai@mentor.com
Huang Yu , Mentor Graphics Corp. Wilsonville, OR 97070. yu_huang@mentor.com
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR 97070. wu-tung_cheng@mentor.com
pp. 1-10

Optical Diagnostics for IBM POWER6- Microprocessor (PDF)

Peilin Song , IBM T.J. Watson Research Center, Yorktown Heights, NY
Stephen Ippolito , IBM Semiconductor Research & Development Center, Hopewell Junction, NY
Franco Stellari , IBM T.J. Watson Research Center, Yorktown Heights, NY
John Sylvestri , IBM Semiconductor Research & Development Center, Hopewell Junction, NY
Tim Diemoz , IBM System and Technology Group, Poughkeepsie, NY
George Smith , IBM System and Technology Group, Poughkeepsie, NY
Paul Muench , IBM System and Technology Group, Poughkeepsie, NY
Norm James , IBM System and Technology Group, Austin, TX
Seongwon Kim , IBM T.J. Watson Research Center, Yorktown Heights, NY
Hector Saenz , IBM System and Technology Group, Austin, TX
pp. 1-9

Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors (PDF)

Tung N. Pham , System and Technology Group Development, IBM, USA
Frances Clougherty , System and Technology Group Development, IBM, USA
Gerard Salem , System and Technology Group Development, IBM, USA
James M. Crafts , System and Technology Group Development, IBM, USA
Jon Tetzloff , System and Technology Group Development, IBM, USA
Pamela Moczygemba , System and Technology Group Development, IBM, USA
Timothy M. Skergan , System and Technology Group Development, IBM, USA
pp. 1-7

Transition Test on UltraSPARC- T2 Microprocessor (PDF)

Kevin Woodling , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Liang-Chi Chen , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085. Liang-Chi.Chen@sun.com
Prasad Mantri , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085. Prasad.Mantri@sun.com
Murali Gala , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085. Murali.Gala@sun.com
Peter Dahlgren , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Subhra Bhattacharya , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Olivier Caty , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Paul Dickinson , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085. Paul.Dickinson@sun.com
Thomas Ziaja , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
David Curwen , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Wendy Yee , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Ellen Su , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Guixiang Gu , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
Tim Nguyen , Sun Microsystem, 410 N. Mary Ave, Sunnyvale, CA 94085
pp. 1-10

DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG (PDF)

Heiko Ahrens , Freescale Semiconductor / STMicroelectronics, München, Germany. heiko.ahrens@freescale.com
Rolf Schlagenhaft , Freescale Semiconductor / STMicroelectronics, München, Germany. rolf.schlagenhaft@freescale.com
Helmut Lang , Freescale Semiconductor / STMicroelectronics, München, Germany. helmut.lang@freescale.com
V. Srinivasan , Freescale Semiconductor / STMicroelectronics, München, Germany. vn.srinivasan@st.com
Enrico Bruzzano , Freescale Semiconductor / STMicroelectronics, München, Germany. enrico.bruzzano@st.com
pp. 1-10

Octal-Site EVM Tests for WLAN Transceivers on "Very" Low-Cost ATE Platforms (PDF)

Ganesh Srinivasan , 12500 TI Boulevard, Texas Instruments Inc., Dallas, Texas. Email: ganeshps@ti.com
Hui-Chuan Chao , 12500 TI Boulevard, Texas Instruments Inc., Dallas, Texas. Email: hchao@ti.com
Friedrich Taenzler , 12500 TI Boulevard, Texas Instruments Inc., Dallas, Texas. Email: ftae@ti.com
pp. 1-9

Optimized EVM Testing for IEEE 802.11a/n RF ICs (PDF)

Erkan Acar , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
Ganesh Srinivasan , Texas Instruments, Dallas, TX
Friedrich Taenzler , Texas Instruments, Dallas, TX
pp. 1-10

EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms (PDF)

V. Natarajan , Georgia Institute of Technology, Atlanta, GA, USA. vishwa@ece.gatech.edu
H. Choi , Georgia Institute of Technology, Atlanta, GA, USA. hyun@ece.gatech.edu
D. Lee , Georgia Institute of Technology, Atlanta, GA, USA. deuk@ece.gatech.edu
R. Senguttuvan , Georgia Institute of Technology, Atlanta, GA, USA. rajs@ece.gatech.edu
A. Chatterjee , Georgia Institute of Technology, Atlanta, GA, USA. chat@ece.gatech.edu
pp. 1-10

Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality (PDF)

Stefan Eichenberger , NXP Semiconductors, Gerstweg 2, FD3, 6534AE Nijmegen, The Netherlands
Jeroen Geuzebroek , NXP Semiconductors, Prof. Holstlaan, HTC-37, 5656AA Eindhoven, The Netherlands
Camelia Hora , NXP Semiconductors, Prof. Holstlaan, HTC-37, 5656AA Eindhoven, The Netherlands
Bram Kruseman , NXP Semiconductors, Prof. Holstlaan, HTC-37, 5656AA Eindhoven, The Netherlands
Ananta Majhi , NXP Semiconductors, Prof. Holstlaan, HTC-37, 5656AA Eindhoven, The Netherlands
pp. 1-10

Modeling Test Escape Rate as a Function of Multiple Coverages (PDF)

Kenneth M. Butler , Texas Instruments, Dallas, TX 75243. kenb@ti.com
John M. Carulli , Texas Instruments, Dallas, TX 75243. jcarulli@ti.com
Jayashree Saxena , External Dev. and Manufacturing/Wireless Terminals Business Unit, Dallas, TX 75243. j-saxena@ti.com
pp. 1-9

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon (PDF)

Yen-Tzu Lin , Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213. yentzul@ece.cmu.edu
Osei Poku , Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213
R. D. Blanton , Department of ECE, Carnegie Mellon University, Pittsburgh PA 15213. blanton@ece.cmu.edu
Phil Nigh , IBM Systems & Technology Group, Essex Junction, VT 05495
Peter Lloyd , IBM Systems & Technology Group, Essex Junction, VT 05495
Vikram Iyengar , IBM Systems & Technology Group, Essex Junction, VT 05495
pp. 1-9

Leveraging IEEE 1641 for Tester-Independent ATE Software (PDF)

Bethany Van Wagenen , Teradyne, Inc. North Reading, MA, U.S.A.
Jon Vollmar , Teradyne, Inc. North Reading, MA, U.S.A.
Dan Thornton , Teradyne, Inc. North Reading, MA, U.S.A.
pp. 1-10

Bridging the gap between Design and Test Engineering for Functional Pattern Development (PDF)

Ernst Aderholz , Freescale Semiconductor, Schatzbogen 7, D-81929 München, +49 89 92103-0. ernst.aderholz@freescale.com
Heiko Ahrens , Freescale Semiconductor, Schatzbogen 7, D-81929 München, +49 89 92103-0. heiko.ahrens@freescale.com
Michael Rohleder , Freescale Semiconductor, Schatzbogen 7, D-81929 München, +49 89 92103-0. michael.rohleder@freescale.com
pp. 1-10

"Plug & Test" at System Level via Testable TLM Primitives (PDF)

Homa Alemzadeh , CAD Research Group, ECE Department, University of Tehran, Tehran 14399, Iran. homa@cad.ece.ut.ac.ir
Stefano Di Carlo , Control and Computer Engineering Department, Politecnico di Torino, I-10129 Torino, Italy. stefano.dicarlo@polito.it
Fatemeh Refan , CAD Research Group, ECE Department, University of Tehran, Tehran 14399, Iran. refan@cad.ece.ut.ac.ir
Paolo Prinetto , Control and Computer Engineering Department, Politecnico di Torino, I-10129 Torino, Italy. paolo.prinetto@polito.it
Zainalabedin Navabi , CAD Research Group, ECE Department, University of Tehran, Tehran 14399, Iran. navabi@cad.ece.ut.ac.ir
pp. 1-10

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits (PDF)

Waleed K. Al-Assadi , Department of Electrical and Computer Engineering, Missouri University of Science and Technology (Missouri S&T), Rolla, MO 65409. Email: waleed@mst.edu
Sindhu Kakarla , Department of Electrical and Computer Engineering, Missouri University of Science and Technology (Missouri S&T), Rolla, MO 65409. Email: sk9qd@mst.edu
pp. 1-9

Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes (PDF)

B. Moore , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada. bmoore@scanimetrics.com
M. Mangrum , Freescale Semiconductors, 7700 West Parmer Lane Austin, Texas 78729, USA
C. Sellathamby , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
M. Reja , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
T. Weng , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
B. Bai , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
E. Reid , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
I. Filanovsky , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, T6G 2V4, Canada
S. Slupsky , Scanimetrics Inc. #4500, 10230 - Jasper Avenue, Edmonton, Alberta, T6J 4P6, Canada
pp. 1-10

On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors (PDF)

Naghmeh Karimi , ECE Department, University of Tehran
Michail Maniatakos , EE Department, Yale University
Abhijit Jas , Validation & Test Solutions, Intel Corporation
Yiorgos Makris , EE & CS Departments, Yale University
pp. 1-10

Using Implications for Online Error Detection (PDF)

K. Nepal , Electrical Engineering Department, Bucknell University, Lewisburg, PA 17837
N. Alves , Division of Engineering, Brown University, Providence, RI 02912
J. Dworak , Division of Engineering, Brown University, Providence, RI 02912
R. I. Bahar , Division of Engineering, Brown University, Providence, RI 02912
pp. 1-10

A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems (PDF)

Syed Z. Shazli , Department of Electrical and Computer Engineering, Northeastern University, Boston MA. Email: sshazli@ece.neu.edu
Mohammed Abdul-Aziz , Department of Electrical and Computer Engineering, Northeastern University, Boston MA. Email: mabdul@ece.neu.edu
Mehdi B. Tahoori , Department of Electrical and Computer Engineering, Northeastern University, Boston MA. Email: mtahoori@ece.neu.edu
David R. Kaeli , Department of Electrical and Computer Engineering, Northeastern University, Boston MA. Email: kaeli@ece.neu.edu
pp. 1-10

Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation (PDF)

A. Katayama , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan. akira4.katayama@toshiba.co.jp
T. Yabe , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
O. Hirabayashi , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
Y. Takeyama , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
K. Kushida , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
T. Sasaki , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
N. Otsuka , Semiconductor Company, Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan
pp. 1-7

A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs (PDF)

Tsu-Wei Tseng , Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320
Jin-Fu Li , Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320
pp. 1-9

Testing Methodology of Embedded DRAMs (PDF)

Chi-Min Chang , Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. cmc.ee95g@nctu.edu.tw
Mango C.-T. Chao , Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. mango@faculty.nctu.edu.tw
Rei-Fu Huang , MediaTek Inc., Hsinchu, Taiwan. rf.huang@mediatek.com
Ding-Yuan Chen , Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan. dingyuan1022@yahoo.com
pp. 1-9

Optimized Circuit Failure Prediction for Aging: Practicality and Promise (PDF)

Varsha Balakrishnan , Arizona State Univ.
Anshuman Bhuyan , Stanford Univ.
Kyunglok Kim , Stanford Univ.
Bipul C. Paul , Stanford Univ.
Wenping Wang , Arizona State Univ.
Bo Yang , Arizona State Univ.
Yu Cao , Arizona State Univ.
Subhasish Mitra , Stanford Univ.
pp. 1-10

SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects (PDF)

Feng Yuan , CUhk REliable computing laboratory (CURE), Dept. of Computer Science & Engineering, The Chinese University of Hong Kong. Email: fyuan@cse.cuhk.edu.hk
Qiang Xu , CUhk REliable computing laboratory (CURE), Dept. of Computer Science & Engineering, The Chinese University of Hong Kong; CAS-CUHK Shenzhen Institute of Advanced Integration Technology. Email: qxu@cse.cuhk.edu.hk
pp. 1-9

Observations of Supply-Voltage-Noise Dispersion in Sub-nsec (PDF)

Kan Takeuchi , Renesas Technology Corp., JAPAN
Genichi Tanaka , Renesas Technology Corp., JAPAN
Hiroaki Matsushita , Renesas Technology Corp., JAPAN
Kenichi Yoshizumi , Hitachi ULSI Systems Co.
Yusaku Katsuki , Hitachi ULSI Systems Co.
Takao Sato , Hitachi ULSI Systems Co.
pp. 1-8

A Hybrid A/D Converter with 120dB SNR and -125dB THD (Abstract)

Mamoru Tamba , Yokogawa Electric Corporation
pp. 1-9

Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production (PDF)

Sadok Aouini , Integrated Microsystems Laboratory, McGill University, 3480 University Street, Montreal, Quebec, CANADA H3A 2A7. Sadok.Aouini@mcgill.ca
Gordon W. Roberts , Integrated Microsystems Laboratory, McGill University, 3480 University Street, Montreal, Quebec, CANADA H3A 2A7. GordonW.Roberts@mcgill.ca
pp. 1-9

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test (PDF)

D. C. Keezer , Georgia Institute of Technology, Atlanta, Georgia, USA
D. Minier , IBM, Bromont, Canada
P. Ducharme , IBM, Bromont, Canada
A. Majid , Georgia Institute of Technology, Atlanta, Georgia, USA
pp. 1-9

On Accelerating Path Delay Fault Simulation of Long Test Sequences (PDF)

I-De Huang , Intel Corp., USA. i-de.huang@intel.com
Yi-Shing Chang , Intel Corp., USA. yi-shing.chang@intel.com
Suriyaprakash Natarajan , Intel Corp., USA. suriyaprakash.natarajan@intel.com
Ramesh Sharma , Intel Corp., USA. ramesh.sharma@intel.com
Sandeep K. Gupta , Electrical Engineering - Systems, University of Southern California, Los Angeles, CA, USA. sandeep@poisson.usc.edu
pp. 1-9

Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model (PDF)

Dheepakkumaran Jayaraman , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901. jayarama@engr.siu.edu
Edward Flanigan , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901. flanigan@engr.siu.edu
Spyros Tragoudas , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901. spyros@engr.siu.edu
pp. 1-10

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects (PDF)

Mahmut Yilmaz , Dept. Electrical and Computer Engineering, Duke University. my@ee.duke.edu
Krishnendu Chakrabarty , Dept. Electrical and Computer Engineering, Duke University. krish@ee.duke.edu
Mohammad Tehranipoor , Dept. Electrical and Computer Engineering, University of Connecticut. tehrani@engr.uconn.edu
pp. 1-10

Boundary-Scan Testing of Power/Ground Pins (PDF)

Kenneth P. Parker , Agilent Technologies and Xilinx Corporation, Loveland, Colorado and San Jose, California. kenneth_parker@agilent.com
Neil G. Jacobson , Agilent Technologies and Xilinx Corporation, Loveland, Colorado and San Jose, California. neil.jacobson@xilinx.com
pp. 1-8

IEEE 1500 Core Wrapper Optimization Techniques and Implementation (PDF)

Brendan Mullane , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland
Michael Higgins , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland
Ciaran MacNamee , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland
pp. 1-10

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard (PDF)

Wei-Shin Wang , Silicon Integrated Systems Corp., Hsinchu, Taiwan
Laung-Terng Wang , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Shianling Wu , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Boryau Sheu , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Kuen-Jong Lee , Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Xiaoqing Wen , Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan
Wen-Ben Jone , Dept. of Electrical and Computer Engineering and Computer Science, University of Cincinnati, OH 45221, USA
Chia-Hsien Yeh , Silicon Integrated Systems Corp., Hsinchu, Taiwan
Ravi Apte , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Hao-Jan Chao , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Jianghao Guo , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA; Dept. of Electrical and Computer Engineering and Computer Science, University of Cincinnati, OH 45221, USA
Jinsong Liu , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Yanlong Niu , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Yi-Chih Sung , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Chi-Chun Wang , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
Fangfang Li , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA
pp. 1-9

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs (PDF)

Zaid Al-Ars , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands. E-mail: z.al-ars@tudelft.nl
Said Hamdioui , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands
Ad J. van de Goor , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands
Georg Mueller , Qimonda AG, Department of Product Engineering, Am Campeon 12, 85579 Neubiberg, Germany
pp. 1-10

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method (PDF)

Jaehoon Joo , Samsung Semiconductor Memory Division, Product Engineering Team, Korea
Junghyun Nam , Yonsei University, Computer System & Reliable Soc Lab, Seoul, Korea
Gibum Koo , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Yanggi Kim , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Byungsoo Moon , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Jonghyoung Lim , Samsung Semiconductor Memory Division, Product Engineering Team, Korea
Sunghoon Chun , Yonsei University, Computer System & Reliable Soc Lab, Seoul, Korea
Sangseok Kang , Samsung Semiconductor Memory Division, Product Engineering Team, Korea
Hoonjung Kim , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Kyeongseon Shin , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Kisang Kang , Samsung Semiconductor Memory Division, Packaging & Test Technologies, Wafer Test Technology Team, Korea
Sungho Kang , Yonsei University, Computer System & Reliable Soc Lab, Seoul, Korea
pp. 1-10

A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories (PDF)

O. Ginez , Aix-Marseille Université, IM2NP, CNRS, IM2NP (UMR 6242), IMT - Technopôle Château Gombert - 13451 Marseille Cedex 20, France. email: Ginez@l2mp.fr
J-M. Portal , Aix-Marseille Université, IM2NP, CNRS, IM2NP (UMR 6242), IMT - Technopôle Château Gombert - 13451 Marseille Cedex 20, France. email: Portal@l2mp.fr
H. Aziza , Aix-Marseille Université, IM2NP, CNRS, IM2NP (UMR 6242), IMT - Technopôle Château Gombert - 13451 Marseille Cedex 20, France. email: Aziza@l2mp.fr
pp. 1-10

Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics (PDF)

Vincent Mao , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Chris Dwyer , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-10

Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates (PDF)

Yang Zhao , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Tao Xu , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1-10

Testing Techniques for Hardware Security (PDF)

Mehrdad Majzoobi , Electrical and Computer Engineering Dept., Rice University, Houston, TX 77005
Farinaz Koushanfar , Electrical and Computer Engineering Dept., Rice University, Houston, TX 77005; Computer Science Dept. Rice University, Houston, TX 77005
Miodrag Potkonjak , Computer Science Dept. University of California Los Angeles, Los Angeles, CA 90095
pp. 1-10

Built-in Self-Calibration of On-chip DAC and ADC (PDF)

Wei Jiang , Electrical and Computer Engineering, Auburn University, Auburn, AL 36849. weijiang@auburn.edu
Vishwani D. Agrawal , Electrical and Computer Engineering, Auburn University, Auburn, AL 36849. vagrawal@eng.auburn.edu
pp. 1-10

A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan. takahiro.yamaguchi@jp.advantest.com
Masayuki Kawabata , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , Department of Electrical Engineering, University of Washington, Seattle, WA
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Kiyotaka Sawami , Advantest Corporation, Kitakyusyu, Fukuoka, Japan
Kouichiro Uekusa , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
pp. 1-9

Test Generation for Interconnect Opens (PDF)

Xijiang Lin , Mentor Graphics Corp., 8005 SW Boeckman Rd, Wilsonville, OR 97068. xijiang_lin@mentor.com
Janusz Rajski , Mentor Graphics Corp., 8005 SW Boeckman Rd, Wilsonville, OR 97068. janusz_rajski@mentor.com
pp. 1-7

A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths (PDF)

Jeremy Lee , ECE Department, University of Connecticut. jslee@engr.uconn.edu
Mohammad Tehranipoor , ECE Department, University of Connecticut. tehrani@engr.uconn.edu
pp. 1-10

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model (PDF)

Stefan Hillebrecht , Computer Architecture Group, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. stspinne@informatik.uni-freiburg.de
Ilia Polian , Computer Architecture Group, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. polian@informatik.uni-freiburg.de
Piet Engelke , Computer Architecture Group, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. engelke@informatik.uni-freiburg.de
Bernd Becker , Computer Architecture Group, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. becker@informatik.uni-freiburg.de
Martin Keim , Mentor Graphics Corp., 8005 SW Boeckman Road, Wilsonville, OR, 97070, USA. martin_keim@mentor.com
Wu-Tung Cheng , Mentor Graphics Corp., 8005 SW Boeckman Road, Wilsonville, OR, 97070, USA. wu-tung_cheng@mentor.com
pp. 1-10

The Advantages of Limiting P1687 to a Restricted Subset (PDF)

Jason Doege , AMD, Austin, TX, USA. jason.doege@amd.com
Alfred L. Crouch , ASSET InterTech, Inc., Cedar Park, TX, USA. acrouch@asset-intertech.com
pp. 1-8

A New Language Approach for IJTAG (PDF)

Michele Portolan , Bell Labs Ireland, Dublin, Ireland
Suresh Goyal , Bell Labs Ireland, Dublin, Ireland
Bradford Van Treuren , Alcatel-Lucent Bell Labs, Murray Hill and Whippany, New Jersey
Chen-Huan Chiang , Alcatel-Lucent Bell Labs, Murray Hill and Whippany, New Jersey
Tapan Chakraborty , Alcatel-Lucent Bell Labs, Murray Hill and Whippany, New Jersey
Thomas B. Cook , Alcatel-Lucent Bell Labs, Murray Hill and Whippany, New Jersey
pp. 1-10

Problems Using Boundary-Scan for Memory Cluster Tests (PDF)

Bradford G. Van Treuren , Alcatel-Lucent, Murray Hill, NJ, USA. vantreuren@alcatel-lucent.com
Chen-Huan Chiang , Alcatel-Lucent, Whippany, NJ, USA. chenhuan@alcatel-lucent.com
Kenneth Honaker , Alcatel-Lucent, Columbus, OH, USA. khonaker@alcatel-lucent.com
pp. 1-10

Increasing Scan Compression by Using X-chains (PDF)

P. Wohl , Synopsys, Inc., wohl@synopsys.com
J.A. Waicukauski , Synopsys, Inc., johnwaic@synopsys.com
F. Neuveux , Synopsys, Inc., fredn@synopsys.com
pp. 1-10

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors (PDF)

Ozgur Sinanoglu , Mathematics and Computer Science Department, Kuwait University, Safat, Kuwait 13060. ozgur@sci.kuniv.edu.kw
pp. 1-10

Launch-on-Shift-Capture Transition Tests (PDF)

Intaik Park , Center for Reliable Computing, Stanford University, Stanford, USA
Edward J. McCluskey , Center for Reliable Computing, Stanford University, Stanford, USA
pp. 1-9

Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps (PDF)

Mike P. Li , Altera, 101 Innovation Drive, San Jose, CA 95134. mpli@altera.com
pp. 1-6

Jitters in high performance microprocessors (PDF)

T.M. Mak , Intel Corporation. t.m.mak@intel.com
pp. 1-6

Embedded Testing in an In-Circuit Test Environment (PDF)

John Malian , Cisco Systems Inc., jmalian@cisco.com
Bill Eklow , Cisco Systems, Inc., beklow@cisco.com
pp. 1-6

Hardware-based Error Rate Testing of Digital Baseband Communication Systems (PDF)

Amirhossein Alimohammad , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB T6G 2V4, Canada
Saeed Fouladi Fard , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB T6G 2V4, Canada
Bruce F. Cockburn , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB T6G 2V4, Canada
pp. 1-10

A Tutorial on STDF Fail Datalog Standard (PDF)

Ajay Khoche , Verigy Pte Ltd. Cupertino, CA - USA
Phil Burlison , Verigy Pte Ltd. Cupertino, CA - USA
John Rowe , Teradyne Inc
Glenn Plowman , Qualcomm
pp. 1-10

Parametric Testing of Optical Interfaces (PDF)

Brice Achkir , Cisco Systems, Inc., bachkir@cisco.com
Pavel Zivny , Tektronix, pzivny@tektronix.com
Bill Eklow , Cisco Systems, Inc., beklow@cisco.com
pp. 1

Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model (PDF)

Scott Davidson , Sun Microsystems, Inc. Sunnyvale, California. scott.davidson@sun.com
pp. 1-10

The Economics of Harm Prevention through Design for Testability (PDF)

Louis Y. Ungar , President, A.T.E. Solutions, Inc., 8939 S. Sepulveda Blvd, Suite 110-779, Los Angeles, CA 90045. Phone: 310-822-5231, Email: LouisUngar@ieee.org
pp. 1-8

Power-Aware DFT - Do we really need it? (PDF)

Nilanjan Mukherjee , Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97007
pp. 1

Power-Aware DFT - Do Not Risk It, Use It (PDF)

Bahram Pouya , Freescale Semiconductor, Inc. Austin, TX
pp. 1

Some Burning Issues that Justify Power-Aware DFT (PDF)

Jeff Rearick , Advanced Micro Devices. jeff.rearick@amd.com
pp. 1

Analog Test Technology: Stable and Grounded, or Open Loop and Spurious (PDF)

Shalabh Goyal , National Semiconductor Corporation, Santa Clara CA USA
pp. 1

Analog Test Technology: Challenges Abound (PDF)

Thomas J Anderson , Teradyne, Inc, San Jose, CA. thomas.anderson@teradyne.com
pp. 1

Will Test Compression Run Out of Gas? (PDF)

Sandeep Kumar Goel , LSI, Advanced Defect Screening Dept., 1621 Barber Lane, M/S AD222, Milpitas, US 95035. sandeep.goel@lsi.com
Erik Jan Marinissen , NXP Semiconductors, Corporate Innovation & Technology/DT&F, High Tech Campus 37, M/S WY 41, 5656 AE Eindhoven, The Netherlands. erik.jan.marinissen@nxp.com
pp. 1

Will Test Compression Run Out of Gas? (PDF)

Sandeep Bhatia , Cadence Design Systems, Inc. San Jose, CA
pp. 1

Will Test Compression Run Out Of Gas? (PDF)

Stephen Pateras , LogicVision, Inc, San Jose, CA
pp. 1

We Need Faster & Deeper Scan and More Realistic Tests (PDF)

Jochen Rivoir , System Architect, Verigy Germany GmbH, Germany
pp. 1-2

The Limits of Compression (PDF)

T. W. Williams , Synopsys Fellow, Synopsys, Inc., Boulder Colorado, USA. E-mail: tww@synopsys.com
pp. 1-2

Debug War Stories (PDF)

LeRoy Winemberg , Freescale Semiconductor, 6501 William Cannon Road, West, MD OE320, Austin, TX 78735. leroyw@freescale.com, (512) 895-7314, Fax (512) 895-6251
pp. 1

Debug War Stories (PDF)

Darrell Carder , Freescale Semiconductor, Austin Texas. darrell.carder@freescale.com
pp. 1

Yield Learning: Everybody Gains, But Who Picks up the Tab? (PDF)

Phil Burlison , Verigy Ltd., 10100 North Tantau Avenue, Cupertino, California 95014. phil.burlison@verigy.com
pp. 1

The University DFT Tool Showdown - Introduction (PDF)

Scott Davidson , Sun Microsystems, Sunnyvale California
pp. 1

Overview of OpenSPARC (PDF)

Ishwar Parulkar , Sun Microsystems. ishwar.parulkar@sun.com
pp. 1

Functional test-bench refinement through automatic constraint extraction (PDF)

Li-C. Wang , University of California, Santa Barbara. licwang@ece.ucsb.edu
Onur Guzey , University of California, Santa Barbara. oguzey@ece.ucsb.edu
pp. 1

Benchmarking Academic DFT Tools on the OpenSparc Microprocessor (PDF)

Ilia Polian , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. polian@informatik.uni-freiburg.de
Christian Miller , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. millerc@informatik.uni-freiburg.de
Piet Engelke , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. engelke@informatik.uni-freiburg.de
Tobias Nopper , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. nopper@informatik.uni-freiburg.de
Alejandro Czutro , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. aczutro@informatik.uni-freiburg.de
Bernd Becker , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-79110 Freiburg i. Br., Germany. becker@informatik.uni-freiburg.de
pp. 1

On the generation of test programs for chip multi-thread computer architectures (PDF)

D. Ravotto , Politecnico di Torino - DAUIN, Corso Duca degli Abruzzi 24, 10129 TORINO - ITALY. danilo.ravotto@polito.it
E. Sanchez , Politecnico di Torino - DAUIN, Corso Duca degli Abruzzi 24, 10129 TORINO - ITALY. ernesto.sanchez@polito.it
M. Sonza Reorda , Politecnico di Torino - DAUIN, Corso Duca degli Abruzzi 24, 10129 TORINO - ITALY. matteo.sonzareorda@polito.it
G. Squillero , Politecnico di Torino - DAUIN, Corso Duca degli Abruzzi 24, 10129 TORINO - ITALY. giovanni.squillero@polito.it
pp. 1

IEEE P1581 drastically simplifies connectivity test for memory devices (PDF)

Heiko Ehrenberg , Chair, IEEE P1581 Working Group, GOEPEL Electronics - Austin, TX / USA. h.ehrenberg@ieee.org
pp. 1

Low Power Test (PDF)

Swapnil Bahl , STMicroelectronics, Pvt. Ltd. Greater Noida, India
Rajiv Sarkar , STMicroelectronics, Pvt. Ltd. Greater Noida, India
Akhil Garg , STMicroelectronics, Pvt. Ltd. Greater Noida, India
pp. 1

IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores (PDF)

Geng-Ming Chiu , Department of Electrical Engineering, National Taiwan University
James Chien-Mo Li , Department of Electrical Engineering, National Taiwan University. cmli@cc.ee.ntu.edu.tw
pp. 1

Test-Access Solutions for Three-Dimensional SOCs (PDF)

Xiaoxia Wu , Computer Science and Engineering Department, The Pennsylvania State University, PA 16802
Yibo Chen , Computer Science and Engineering Department, The Pennsylvania State University, PA 16802
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708
Yuan Xie , Computer Science and Engineering Department, The Pennsylvania State University, PA 16802
pp. 1

SOC Test Optimization with Compression-Technique Selection (PDF)

Anders Larsson , Dep. of Computer Science, Linköping University, SE-582 83 Linköping, Sweden
Xin Zhang , Dep. of Computer Science, Linköping University, SE-582 83 Linköping, Sweden
Erik Larsson , Dep. of Computer Science, Linköping University, SE-582 83 Linköping, Sweden
Krishnendu Chakrabarty , Dep. of Electrical and Computer Engineering, Duke University, Durham NC 27708, USA
pp. 1

SoC Yield Improvement: Redundant Architectures to the Rescue? (PDF)

J. Vial , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: vial@lirmm.fr
A. Bosio , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: bosio@lirmm.fr
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: girard@lirmm.fr
C. Landrault , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: landraul@lirmm.fr
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: pravo@lirmm.fr
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - Univ. Montpellier / CNRS, 161, rue Ada 34932 Montpellier - France. Email: virazel@lirmm.fr
pp. 1

Platform Independent Test Access Port Architecture (PDF)

Arie Margulis , AMD Markham, ON, Canada
Dimitry Akselrod , McMaster Univ., ON, Canada
Tim Wood , AMD Austin, TX
Sophocles Metsis , AMD Boxborough, MA
pp. 1

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure (PDF)

Armin Alaghi , Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
Mahshid Sedghi , Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
Naghmeh Karimi , Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
Zainalabedin Navabi , Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
pp. 1

VLSI Test Exercise Courses for Students in EE Department (PDF)

Satoshi Komatsu , VLSI Design and Education Center, University of Tokyo, Tokyo, Japan
pp. 1

Hardware Overhead Reduction for Memory BIST (PDF)

Masayuki Arai , Tokyo Metropolitan University, Tokyo, Japan
Kazuhiko Iwasaki , Tokyo Metropolitan University, Tokyo, Japan
Michinobu Nakao , Renesas Technology Corp., Tokyo, Japan
Iwao Suzuki , Renesas Technology Corp., Tokyo, Japan
pp. 1

A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances (PDF)

Chung-Fu Lin , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
Chia-Fu Huang , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
De-Chung Lu , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
Chih-Chiang Hsu , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
Wen-Tsung Chiu , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
Yu-Wei Chen , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
Yeong-Jar Chang , Faraday Technology Corporation, Hsinchu City, Taiwan, R.O.C.
pp. 1

The Importance of Functional-Like Access for Memory Test (PDF)

Jonathan Phelps , Texas Instruments, 12500 TI Boulevard, M/S 8645, Dallas, TX 75243. E-mail: jphelps@ti.com
Chuck Johnson , Texas Instruments, 12500 TI Boulevard, M/S 8645, Dallas, TX 75243. E-mail: chuck.johnson@ti.com
Corey Goodrich , Texas Instruments, 12500 TI Boulevard, M/S 8645, Dallas, TX 75243. E-mail: coreyg@ti.com
Aman Kokrady , Texas Instruments, 12500 TI Boulevard, M/S 8645, Dallas, TX 75243. E-mail: koko@ti.com
pp. 1

An Efficient Secure Scan Design for an SoC Embedding AES Core (PDF)

Jaehoon Song , Department of Computer Science & Engineering, Hanyang University, Korea
Taejin Jung , Department of Computer Science & Engineering, Hanyang University, Korea
Junseop Lee , Department of Computer Science & Engineering, Hanyang University, Korea
Hyeran Jeong , Department of Computer Science & Engineering, Hanyang University, Korea
Byeongjin Kim , Department of Computer Science & Engineering, Hanyang University, Korea
Sungju Park , Department of Computer Science & Engineering, Hanyang University, Korea
pp. 1

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains (PDF)

Jing Ye , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, CAS, Beijing 100190, China; Graduate University of Chinese Academy of Sciences, Beijing 100190, China
Fei Wang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, CAS, Beijing 100190, China; Graduate University of Chinese Academy of Sciences, Beijing 100190, China
Yu Hu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, CAS, Beijing 100190, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, CAS, Beijing 100190, China
pp. 1

Diagnosis of Logic-to-chain Bridging Faults (PDF)

Wei-Chih Liu , Department of Electrical Engineering, National Taiwan University
Wei-Lin Tsai , Department of Electrical Engineering, National Taiwan University
Hsiu-Ting Lin , Department of Electrical Engineering, National Taiwan University
James Chien-Mo Li , Department of Electrical Engineering, National Taiwan University. cmli@cc.ee.ntu.edu.tw
pp. 1

Power Distribution Failure Analysis Using Transition-Delay Fault Patterns (PDF)

Junxia Ma , ECE Dept., University of Connecticut, Storrs, CT. junxia@engr.uconn.edu
Jeremy Lee , ECE Dept., University of Connecticut, Storrs, CT. jslee@engr.uconn.edu
Mohammad Tehranipoor , ECE Dept., University of Connecticut, Storrs, CT. tehrani@engr.uconn.edu
pp. 1

Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy? (PDF)

Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: lhuang@cse.cuhk.edu.hk
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: qxu@cse.cuhk.edu.hk
pp. 1

System JTAG Initiative Group Advancements (PDF)

Bradford G. Van Treuren , SJTAG Initiative Chairman, Alcatel-Lucent Murray Hill, New Jersey
pp. 1

A Generic Framework for Scan Capture Power Reduction in Test Compression Environment (PDF)

Xiao Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: xliu@cse.cuhk.edu.hk
Feng Yuan , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: fyuan@cse.cuhk.edu.hk
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: qxu@cse.cuhk.edu.hk
pp. 1

High Test Quality in Low Pin Count Applications (PDF)

Jayant D'Souza , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA Ph# +1 (503) 685 7023, jayant_dsouza@mentor.com
Subramanian Mahadevan , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA Ph# +1 (503) 685 7023, subramanian_mahadevan@mentor.com
Nilanjan Mukherjee , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA Ph# +1 (503) 685 7023, nilanjan_mukherjee@mentor.com
Graham Rhodes , Mentor Graphics (France) S.a.r.l. Immeuble « Le Pasteur » 13/15, rue Jeanne Bracconnier 92360 Meudon La Foret - France. graham_rhodes@mentor.com
Jocelyn Moreau , ST Microelectronics, 12, Rue Jules Horowitz - B.P.217, F-38019 GRENOBLE CedexNo. 3, Ph# +33 (0) 4 76 58 50 00, jocelyn.moreau@st.com
Thomas Droniou , ST Microelectronics, 12, Rue Jules Horowitz - B.P.217, F-38019 GRENOBLE CedexNo. 3, Ph# +33 (0) 4 76 58 50 00, thomas.droniou@st.com
Paul Armagnat , ST Microelectronics, 12, Rue Jules Horowitz - B.P.217, F-38019 GRENOBLE CedexNo. 3, Ph# +33 (0) 4 76 58 50 00, paul.armagnati@st.com
pp. 1

Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise (PDF)

Hsiu-Ting Lin , Graduate Institute of Electronics Engineering, National Taiwan University
Jen-Yang Wen , Graduate Institute of Electronics Engineering, National Taiwan University
James Li , Graduate Institute of Electronics Engineering, National Taiwan University
Ming-Tung Chang , Global Unichip Corporation, Hsinchu, Taiwan
Min-Hsiu Tsai , Global Unichip Corporation, Hsinchu, Taiwan
Sheng-Chih Huang , Global Unichip Corporation, Hsinchu, Taiwan
Chih-Mou Tseng , Global Unichip Corporation, Hsinchu, Taiwan
pp. 1

Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study (PDF)

Che-Jen Jerry Chang , SMTS, ASIC design, DTV Division, AMD, 33 Commerce Valley Dr. East, Markham, ON, L3T 3N6. jerry.chang@amd.com, Ph# +1 (905) 882 2600 ext 2117, FAX# +1 (905) 882 2567
Takeo Kobayashi , Technical Marketing Engineer, Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070. takeo_kobayashi@mentor.com, Ph# +1 (503) 685 1833, FAX# +1 (503) 685 4729
pp. 1

FPGA Time Measurement Module: Preliminary Results (PDF)

William J. Bowhers , Merrimack College, North Andover, MA, USA
pp. 1

Wireless Test Structure for Integrated Systems (PDF)

Ziad Noun , NXP Semiconductors, CAEN, France
Philippe Cauvet , NXP Semiconductors, CAEN, France
Marie-Lise Flottes , LIRMM, University of Montpellier / CNRS, Montpellier, France
David Andreu , LIRMM, University of Montpellier / CNRS, Montpellier, France
Serge Bernard , LIRMM, University of Montpellier / CNRS, Montpellier, France
pp. 1

Overview of a High Speed Top Side Socket Solution (PDF)

John Stewart , JF4-205 Intel Corporation, Hillsboro, Oregon, United States. john.c.stewart@intel.com, 503-264-6403
Temitope Animashaun , JF4-205 Intel Corporation, Hillsboro, Oregon, United States. temitope.animashaun@intel.com, 503-712-6463
pp. 1

Improving the Accuracy of Test Compaction through Adaptive Test Update (PDF)

Sounil Biswas , Nvidia Corp., Santa Clara, CA 95050. sbiswas@nvidia.com
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA 15213. blanton@ece.cmu.edu
pp. 1

On-chip Timing Uncertainty Measurements on IBM Microprocessors (PDF)

R. Franch , IBM Research, Yorktown Heights, NY
P. Restle , IBM Research, Yorktown Heights, NY
N. James , IBM STG, Austin, TX
W. Huott , IBM STG, Poughkeepsie, NY
J. Friedrich , IBM STG, Austin, TX
R. Dixon , IBM STG, Austin, TX
S. Weitzel , IBM STG, Austin, TX
K. Van Goor , IBM STG, Rochester, MN
G. Salem , IBM STG, Burlington, VT
pp. 1-7

DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs (PDF)

Amit Dutta , Texas Instruments, Bangalore, India
Srinivasulu Alampaily , Texas Instruments, Bangalore, India
Prasanth V , Texas Instruments, Bangalore, India
Rubin A. Parekhji , Texas Instruments, Bangalore, India
pp. 1-10

Robust Design-for-Productization Practices for High Quality Automotive Products (PDF)

Paolo Bernardi , Politecnico 2di Torino, Dipartimento di Automatica ed Infontnatica, Italy
Fabio Melchiori , STMicroelectronics S.r.l., Agrate Brianza, Italy
Davide Pandini , STMicroelectronics S.r.l., Agrate Brianza, Italy
Santo Pugliese , STMicroelectronics S.r.l., Agrate Brianza, Italy
Davide Appello , STMicroelectronics S.r.l., Agrate Brianza, Italy
pp. 1-9
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