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2013 IEEE International Test Conference (ITC) (2005)
Austin, TX, USA
Nov. 8, 2005 to Nov. 8, 2005
ISBN: 0-7803-9038-5
pp: 10 pp.-696
ABSTRACT
Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques.
INDEX TERMS
built-in soft error resilience, logic soft errors, radiation induced soft errors, flip flops, power overhead, performance overheads, fault tolerance techniques, design-for-functional-test, debug resources
CITATION
T.M. Mak, null Kee Sup Kim, V. Zia, S. Mitra, null Ming Zhang, N. Seifert, "Logic soft errors: a major barrier to robust platform design", 2013 IEEE International Test Conference (ITC), vol. 00, no. , pp. 10 pp.-696, 2005, doi:10.1109/TEST.2005.1584031
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