The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2004)
Charlotte, NC, USA
Oct. 26, 2004 to Oct. 28, 2004
ISSN: 1089-3539
ISBN: 0-7803-8581-0
TABLE OF CONTENTS
Cover
Introduction
SESSION 1: PLENARY
SESSION 2: MICROPROCESSOR TEST

AC IO Loopback Design for High Speed uProcessor IO Test (Abstract)

Benoit Provost , Intel Corporation. Hillsboro, OR, USA
Cangsang Zhao , Intel Corporation. Santa Clara, CA, USA
Tiffany Huang , Intel Corporation. Santa Clara, CA, USA
Kathy Tian , Intel Corporation. Santa Clara, CA, USA
Mo Bashir , Intel Corporation. Hillsboro, OR, USA
Mubeen Atha , Intel Corporation. Santa Clara, CA, USA
Chee How Lim , Intel Corporation. Hillsboro, OR, USA
Ali Muhtaroglu , Intel Corporation. Hillsboro, OR, USA
Harry Muljono , Intel Corporation. Santa Clara, CA, USA
pp. 23-30

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design (Abstract)

J. Abraham , University of Texas at Austin, Austin, TX
A. Kolhatkar , Freescale Semiconductor Inc., Austin, TX
L. Wang , University of California, Santa Barbara, CA
J. Zeng , Freescale Semiconductor Inc., Austin, TX
G. Vandling , Cadence Design Systems, Endicott, NY
M. Abadir , Freescale Semiconductor Inc., Austin, TX
pp. 31-37

An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor (Abstract)

Larry Thatcher , Intel Corporation
Madhukar Reddy , Intel Corporation
Anil Sabbavarapu , Intel Corporation
David M. Wu , Intel Corporation
Mike Lin , Intel Corporation
Talal Jaber , Intel Corporation
pp. 38-47
SESSION 3: LOGIC BIST

EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BIST (Abstract)

Harald Vranken , Philips Research, Netherlands
Michael Garbers , Philips Semiconductors, Germany
Valentin Gherman , Universitat Stuttgart, Germany
Friedrich Hapke , Philips Semiconductors, Germany
Hans-Joachim Wunderlich , Universitat Stuttgart, Germany
Michael Wittke , Philips Semiconductors, Germany
pp. 48-56

Logic BISTWith Scan Chain Segmentation (Abstract)

Thomas Rinderknecht , Mentor Graphics Corp., OR
Liyang Lai , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
Wu-Tung Cheng , Mentor Graphics Corp., OR
pp. 57-66
SESSION 4: BIST FOR JITTER

A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems (Abstract)

Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Katsuaki Ohsawa , Advantest Corporation, Gunma, Japan
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Kiyotaka Ichiyama , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , University of Washington, Seattle, WA
Krawinkel Christian , Advantest Corporation, Gunma, Japan
Masao Sugai , Advantest Corporation, Gunma, Japan
pp. 77-84

Experimental Results for High-Speed Jitter Measurement Technique (Abstract)

Hieu Nguyen , University of Washington, Seattle, WA
Henry Lin , University of Washington, Seattle, WA
Alan Chong , University of Washington, Seattle, WA
Bryan Nelson , University of Washington, Seattle, WA
Karen Taylor , University of Washington, Seattle, WA
Hosam Haggag , Santa Clara Design Center, National Semiconductor, Santa Clara, CA
Jim Braatz , Tacoma Design Center, National Semiconductor, Federal Way, WA
Mani Soma , University of Washington, Seattle, WA
Jeff Huard , Tacoma Design Center, National Semiconductor, Federal Way, WA
pp. 85-94

An Automated, Complete, Structural Test Solution for SERDES (Abstract)

Aubin Roy , LogicVision, Inc.
Stephen Sunter , LogicVision, Inc.
J-F Cote , LogicVision, Inc.
pp. 95-104
SESSION 5: MEMORY TESTING

A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis (Abstract)

Vishnumohan Ravichandran , Intel Corporation, Hillsboro, OR, USA
Benjamin M. Mauck , Intel Corporation, Hillsboro, OR, USA
Usman Azeez Mughal , Intel Corporation, Hillsboro, OR, USA
pp. 105-113

DETECTING FAULTS IN THE PERIPHERAL CIRCUITS AND AN EVALUATION OF SRAM TESTS (Abstract)

Ad J. Van de Goor , Delft University of Technology, Netherlands
Rob Wadsworth , ST Microlelctronics, Carrollton, TX
Said Hamdioui , Philips Semiconductor R&D, France
pp. 114-123

MRAM Defect Analysis and Fault Modeli (Abstract)

Cheng-Wen Wu , National Tsing Hua University Hsinchu, Taiwan
Chin-Lung Su , National Tsing Hua University Hsinchu, Taiwan
Yeong-Jar Chang , SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan
Chien-Chung Hung , Industrial Technology Research Institute Hsinchu, Taiwan
Ming-Jer Kao , Industrial Technology Research Institute Hsinchu, Taiwan
Wen-Ching Wu , SoC Technology Center, Industrial Technology Research Institute Hsinchu, Taiwan
Rei-Fu Huang , National Tsing Hua University Hsinchu, Taiwan
pp. 124-133
SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS

CMOS IC diagnostics using the luminescence of OFF-state leakage currents (Abstract)

Alan Weger , IBM T.J. Watson Research Center, NY
Shinho Cho , Silla University, S. Korea
Stas Polonsky , IBM T.J. Watson Research Center, NY
Keith A. Jenkins , IBM T.J. Watson Research Center, NY
pp. 134-139

A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current (Abstract)

Peilin Song , IBM T.J. Watson Research Center, Yorktown Heights, NY
Alan J. Weger , IBM T.J. Watson Research Center, Yorktown Heights, NY
Tian Xia , University of Vermont, Burlington, VT
Franco Stellari , IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 140-147

IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON PRODUCT PARAMETRIC DRIFT (Abstract)

Anand Krishnan , Texas Instruments Inc.
William Bosch , Texas Instruments Inc., Stafford, TX
Vijay Reddy , Texas Instruments Inc.
John Carulli , Texas Instruments Inc.
Brendan Burgess , Texas Instruments Inc., Stafford, TX
pp. 148-155
SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE

At-Speed Interconnect Test and Diagnosis of External Memories on a System (Abstract)

Hong-Shin Jun , Cisco Systems, Inc.
Heon C. Kim , Cisco Systems, Inc.
Sung S. Chung , Cisco Systems, Inc.
Xinli Gu , Cisco Systems, Inc.
pp. 156-162

Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors (Abstract)

Mehrdad Nourani , University of Texas at Dallas, Richardson, TX
Kendrick Baker , Raytheon Company, Plano, TX
pp. 163-172

Removing JTAG Bottlenecks in System Interconnect Test (Abstract)

Sung S. Chung , Cisco Systems, Inc., Tasman Drive San Jose, CA
Sang H. Baeg , Cisco Systems, Inc., Tasman Drive San Jose, CA
Hong-Shin Jun , Cisco Systems, Inc., Tasman Drive San Jose, CA
pp. 173-180
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST

ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test (Abstract)

Manu Rehani , LSI Logic Corporation
Robert Madge , LSI Logic Corporation
Jason Saw , Invantest Corporation, San Jose, CA, USA
David Abercrombie , LSI Logic Corporation
Jim Teisher , LSI Logic Corporation
pp. 181-189

NON-DETERMINISTIC DUT BEHAVIOR DURING FUNCTIONAL TESTING OF HIGH SPEED SERIAL BUSSES: CHALLENGES AND SOLUTIONS (Abstract)

Brian Swing , Semiconductor Test, Teradyne Inc., Boston, MA
Jonathan Hops , Semiconductor Test, Teradyne Inc., Boston, MA
John Pane , Semiconductor Test, Teradyne Inc., Boston, MA
Brian Phelps , Semiconductor Test, Teradyne Inc., Boston, MA
James Kinslow , Semiconductor Test, Teradyne Inc., Boston, MA
Bruce Sudweeks , Semiconductor Test, Teradyne Inc., Boston, MA
pp. 190-196

Divide and Conquer based Fast Shmoo algorithms (Abstract)

Peter Patten , Agilent Technologies, Germany
pp. 197-202

IN SEARCH OF THE OPTIMUM TEST SET - ADAPTIVE TEST METHODS FOR MAXIMUM DEFECT COVERAGE AND LOWEST TEST COST (Abstract)

Robert Madge , LSI Logic Corporation, Gresham, Oregon
Chris Schuermyer , Portland State University, Portland, Oregon
Ritesh Turakhia , LSI Logic Corporation, Ft. Collins, Colorado
Brady Benware , LSI Logic Corporation, Ft. Collins, Colorado
Robert Daasch , Portland State University, Portland, Oregon
Jens Ruffler , Portland State University, Portland, Oregon
pp. 203-212
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS

On Hazard-free Patterns for Fine-delay Fault Testing (Abstract)

Guido Gronthoud , Philips Research, Netherlands
Bram Kruseman , Philips Research, Netherlands
Stefan Eichenberger , Philips Semiconductor, Netherlands
Ananta K. Majhi , Philips Research, Netherlands
pp. 213-222

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits (Abstract)

D. M. H. Walker , Texas A&M University, College Station, TX
Divya Reddy , Texas Instruments, Inc.
Hari Balachandran , Texas Instruments, Inc.
Jing Wang , Texas A&M University, College Station, TX
Zhuo Li , Dept. of Electrical Engineering, Texas A&M University, College Station, TX
Wangqi Qiu , Texas A&M University, College Station, TX
Weiping Shi , Dept. of Electrical Engineering, Texas A&M University, College Station, TX
pp. 223-231

A Critical Path Selection Method for Delay Testing (Abstract)

Spyros Tragoudas , Southern Illinois University, Carbondale, IL
Saravanan Padmanaban , Intel Corporation, Hillsboro, OR
pp. 232-241

Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study (Abstract)

Haihua Yan , Auburn University, Auburn, AL
Adit D. Singh , Auburn University, Auburn, AL
pp. 242-251
SESSION 10: MIXED-SIGNAL BIST AND DFT

Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters (Abstract)

Ashwin Raghunathan , University of Texas at Austin, TX
Jacob A. Abraham , University of Texas at Austin, TX
Ji Hwan Chun , University of Texas at Austin, TX
Abhijit Chatterjee , Georgia Institute of Technology
pp. 252-261

On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing (Abstract)

Chintan Patel , University of Maryland, Baltimore County
Abhishek Singh , University of Maryland, Baltimore County
Jim Plusquellic , University of Maryland, Baltimore County
pp. 262-270

AUTOMATIC LINEARITY (IP3) TEST WITH BUILT-IN PATTERN GENERATOR AND ANALYZER (Abstract)

Charles Stroud , Auburn University, Auburn, AL
Dayu Yang , Auburn University, Auburn, AL
Foster Dai , Auburn University, Auburn, AL
Shuying Qi , Auburn University, Auburn, AL
pp. 271-280

Extending the Digital Core-based Test Methodology to Support Mixed-Signal (Abstract)

Geert Seuren , Philips Research Electronics Design, Netherlands
Tom Waayers , Philips Research Electronics Design, Netherlands
pp. 281-289
SESSION 11: ADVANCES IN TESTING FOR DEFECTS

Systematic Defects in Deep Sub-Micron Technologies (Abstract)

Ananta Majhi , Philips Research Laboratories, Netherlands
Bram Kruseman , Philips Research Laboratories, Netherlands
Camelia Hora , Philips Research Laboratories, Netherlands
Stefan Eichenberger , Philips Semiconductors, Netherlands
Johan Meirlevede , Philips Semiconductors, Netherlands
pp. 290-299

MINIMUM TESTING REQUIREMENTS TO SCREEN TEMPERATURE DEPENDENT DEFECTS (Abstract)

J. Ruffler , LSI Logic Corporation, Gresham, OR
R. Daasch , LSI Logic Corporation, Gresham, OR
C. Schuermyer , LSI Logic Corporation, Gresham, OR
pp. 300-308

Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement (Abstract)

Chintan Patel , University of Maryland, Baltimore, MD
Abhishek Singh , University of Maryland, Baltimore, MD
Jim Plusquellic , University of Maryland, Baltimore, MD
pp. 319-328
SESSION 12: ADVANCES IN DFT

Testing Micropipelined Asynchronous Circuits (Abstract)

Matthew L. King , University of Wisconsin - Madison
Kewal K. Saluja , University of Wisconsin - Madison
pp. 329-338

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard (Abstract)

Bo Yang , Polytechnic University, Brooklyn, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
Ramesh Karri , Polytechnic University, Brooklyn, NY
pp. 339-344

A Holistic Parallel and Hierarchical Approach towards Design-For-Test (Abstract)

C. P. Ravikumar , Texas Instrument (India)
G. Hetherington , Texas Instrument Ltd, United Kingdom
pp. 345-354

Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques (Abstract)

Jayashree Saxena , Texas Instruments Inc., Dallas
Graham Hetherington , Texas Instruments Inc., Dallas
Tony Fryars , Texas Instruments Inc., Dallas
Kenneth M. Butler , Texas Instruments Inc., Dallas
pp. 355-364
SESSION 13: BOARD AND SYSTEM TEST: BOARD TEST EFFECTIVENESS

On-Chip Mixed-Signal Test Structures Re-used for Board Test (Abstract)

A. Kumar , Indian Institute of Technology, Delhi, India
R. Schuttert , Philips Research, Netherlands
D.C.L. Van Geest , Philips Research, Netherlands
pp. 375-383

Test Strategy Cost Model Innovations (Abstract)

Carlos Michel , Hewlett-Packard Company, Jalisco, Mexico
Rosa D. Reinosa , Hewlett-Packard Company, Palo Alto, California, USA
pp. 384-392

Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies (Abstract)

Steve Butkovich , Cisco Systems, Inc.
Amit Verma , Rapiscan Security Products
Charles Robinson , Teradyne Inc.
pp. 393-402
SESSION 14: DEVELOPMENTS IN ATE SOFTWARE STANDARDS

Open Architecture Test System: System Architecture and Design (Abstract)

Masuda Noriyuki , Advantest Corporation, Gunma, Japan
Rochit Rajsuman , Advantest America Corporation
pp. 403-412

TEST PROGRAMMING ENVIRONMENT IN A MODULAR, OPEN ARCHITECTURE TEST SYSTEM (Abstract)

Bruce Parnas , Advantest America R&D Center Inc., Santa Clara, CA
Ramachandran Krishnaswamy , Advantest America R&D Center Inc., Santa Clara, CA
Ankan Pramanick , Advantest America R&D Center Inc., Santa Clara, CA
Harsanjeet Singh , Advantest America R&D Center Inc., Santa Clara, CA
Toshiaki Adachi , Advantest America R&D Center Inc., Santa Clara, CA
Mark Elston , Advantest America R&D Center Inc., Santa Clara, CA
pp. 413-422

Extending STIL 1450 Standard for Test Program Flow (Abstract)

Ernie Wahl , Agere Systems Allentown, PA. USA
Don Organ , Inovys Corporation Pleasanton, CA. USA
David Dowding , Agilent Technologies, Inc. Loveland, CO. USA
pp. 423-431
SESSION 15: HANDLING OF UNKNOWNS

X-TOLERANT SIGNATURE ANALYSIS (Abstract)

Subhasish Mitra , Intel Corporation Folsom, CA
Michael Mitzenmacher , Harvard University
Steven S. Lumetta , Univ. of Illinois, Urbana-Champaign
pp. 432-441

X-Masking During Logic BIST and Its Impact on Defect Coverage (Abstract)

Harald Vranken , Philips Research Laboratories, The Netherlands
Bernd Becker , Albert-Ludwigs-University, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Germany
Yuyi Tang , University of Stuttgart, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
Friedrich Hapke , Philips Semiconductors GmbH, Hamburg, Germany
Piet Engelke , Albert-Ludwigs-University, Germany
Michael Wittke , Philips Semiconductors GmbH, Hamburg, Germany
pp. 442-451

Channel Masking Synthesis for Efficient On-Chip Test Compression (Abstract)

Vivek Chickermane , Cadence Design Systems, Endicott, NY, USA
Brion Keller , Cadence Design Systems, Endicott, NY, USA
Brian Foutz , Cadence Design Systems, Endicott, NY, USA
pp. 452-461
SESSION 16: EMERGING TECHNOLOGIES FAULT MODELING and TOLERANCE

CAEN-BIST: Testing the NanoFabric (Abstract)

Jason G. Brown , Carnegie Mellon University, Pittsburgh PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh PA
pp. 462-471

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems (Abstract)

Wenjing Rao , UC San Diego
Alex Orailoglu , UC San Diego
Ramesh Karri , India Polytechnic University, India
pp. 472-478

Routability and Fault Tolerance of FPGA Interconnect Architectures (Abstract)

Mehdi Baradaran Tahoori , Northeastern University Boston, MA
Jing Huang , Northeastern University Boston, MA
Fabrizio Lombardi , Northeastern University Boston, MA
pp. 479-488
SESSION 17: ADVANCES IN DIAGNOSIS

Z-DFD: DESIGN-FOR-DIAGNOSABILITY BASED ON THE CONCEPT OF Z-DETECTION (Abstract)

Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City, IA
pp. 489-497

FAULT DIAGNOSIS IN DESIGNSWITH CONVOLUTIONAL COMPACTORS (Abstract)

Grzegorz Mrugalski , Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Chen Wang , Mentor Graphics Corporation, Wilsonville, OR
Artur Pogiel , Poznan University of Technology, Poland
Jerzy Tyszer , Poznan University of Technology, Poland
pp. 498-507

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations (Abstract)

W. Maly , Carnegie Mellon University, Pittsburgh, PA
Y. Fei , Carnegie Mellon University, Pittsburgh, PA
V. Rovner , Carnegie Mellon University, Pittsburgh, PA
R. Desineni , Carnegie Mellon University, Pittsburgh, PA
T. Zanon , Carnegie Mellon University, Pittsburgh, PA
P. Gopalakrishnan , Carnegie Mellon University, Pittsburgh, PA
M. Mishra , Carnegie Mellon University, Pittsburgh, PA
S. Tiwary , Carnegie Mellon University, Pittsburgh, PA
J. G. Brown , Carnegie Mellon University, Pittsburgh, PA
J. E. Nelson , Carnegie Mellon University, Pittsburgh, PA
T. Vogels , Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
X. Huang , Carnegie Mellon University, Pittsburgh, PA
pp. 508-517
SESSION 18: TEST ECONOMICS

An Economic Analysis and ROI Model for Nanometer Test (Abstract)

Mick Tegethoff , Cadence Design Systems, Inc Endicott, NY
Brion Keller , Cadence Design Systems, Inc Endicott, NY
Thomas Bartenstein , Cadence Design Systems, Inc Endicott, NY
Vivek Chickermane , Cadence Design Systems, Inc Endicott, NY
pp. 518-524

Realizing High Test Quality Goals with Smart Test Resource Usage (Abstract)

Cyndee Wang , Cisco Systems, Inc., San Jose, CA
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Jan A. Tofte , Mentor Graphics Corporation, Wilsonville, OR
Bill Eklow , Cisco Systems, Inc., San Jose, CA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR
Xinli Gu , Cisco Systems, Inc., San Jose, CA
Abby Lee , Cisco Systems, Inc., San Jose, CA
pp. 525-533

LOW OVERHEAD DELAY TESTING OF ASICS (Abstract)

Francis Woytowich , IBM Corporation Essex Junction, VT
Pamela Gillis , IBM Corporation Essex Junction, VT
Andrew Ferko , IBM Corporation Essex Junction, VT
Kevin McCauley , Cadence Design Systems Endicott, NY
pp. 534-542
SESSION 19: BOARD AND SYSTEM TEST: EXTENDING BOUNDARY-SCAN TO RF AND HS SERIAL TESTING

A FREQUENCY MIXING AND SUB-SAMPLING BASED RF-MEASUREMENT APPARATUS FOR IEEE 1149.4 (Abstract)

Pekka Syri , Electrical and Information Engineering, Electronics Laboratory, University of Oulu, Finland
Juha Hakkinen , Electrical and Information Engineering, Electronics Laboratory, University of Oulu, Finland
Markku Moilanen , Optoelectronics and Measurement Techniques Laboratory, University of Oulu, Finland
Juha-Veikko Voutilainen , Optoelectronics and Measurement Techniques Laboratory, University of Oulu, Finland
pp. 551-559

Integrating Boundary Scan into Multi-GHz I/O Circuitry (Abstract)

Krista Dorner , Agilent Technologies ASIC Product Division Fort Collins, CO
Sylvia Patterson , Agilent Technologies ASIC Product Division Fort Collins, CO
Jeff Rearick , Agilent Technologies ASIC Product Division Fort Collins, CO
pp. 560-566
SESSION 20: SQUEEZING THE PICOSECONDS

Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE (Abstract)

Masashi Shimanouchi , Credence Systems, Baytech Drive, San Jose, CA
pp. 567-576

Automatic Delay Calibration Method for Multi-channel CMOS Formatter (Abstract)

Ahmed Rashid Syed , Credence Systems Corporation, Baytech Dr. San Jose, CA
pp. 577-586

Active Tester Interface Unit Design For Data Collection (Abstract)

A.T. Sivaram , Credence Inc Intel, Baytech Drive, San Jose, CA
Nancy Wang-Lee , Intel Corporation, Chandler, AZ
Lily Tran , Intel Corporation, Chandler, AZ
Pascal Pierra , Credence Inc Intel, Baytech Drive, San Jose, CA
Jorge E. Solorzano , Intel Corporation, Chandler, AZ
Shida Sheibani , Credence Inc Intel, Baytech Drive, San Jose, CA
pp. 587-596
SESSION 21: ATPG/FAULT SIMULATION SPECIALTIES

SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits (Abstract)

Yiorgos Makris , Yale University New Haven, CT
Feng Shi , Yale University New Haven, CT
pp. 597-606

Decision Selection and Learning for an ?All-Solutions ATPG Engine (PDF)

Michael S. Hsiao , Virginia Tech, Blacksburg, VA
Kameshwar Chandrasekar , Virginia Tech, Blacksburg, VA
pp. 607-616

On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits (Abstract)

Michael L. Bushnell , Rutgers University, Piscataway, NJ
Junwu Zhang , Rutgers University, Piscataway, NJ
Vishwani D. Agrawal , Auburn University, AL
pp. 617-626
SESSION 22: INTERCONNECT TESTING AND FAULT DIAGNOSIS IN FPGAS

Localizing Open Interconnect Defects using Targeted Routing in FPGA?s (Abstract)

Dave Mark , xilinx.com Logic Dr. San Jose, CA
Jenny Fan , xilinx.com Logic Dr. San Jose, CA
pp. 627-634

Interconnect Delay Testing of Designs on Programmable Logic Devices (Abstract)

Mehdi Baradaran Tahoori , Northeastern University Boston, MA
Subhasish Mitra , Intel Corporation Sacramento, CA
pp. 635-644

Application-Dependent Diagnosis of FPGAs (Abstract)

Mehdi Baradaran Tahoori , Northeastern University Boston, MA
pp. 645-654
SESSION 23: INDUSTRY CASE STUDIES IN TESTING

Feed Forward Test Methodology Utilizing Device Identification (Abstract)

A. Cabbibo , LSI Logic Corporation, Gresham, Oregon
J. Conder , LSI Logic Corporation, Gresham, Oregon
M. Jacobs , LSI Logic Corporation, Gresham, Oregon
pp. 655-660

Data Mining Integrated Circuit Fails with Fail Commonalities (Abstract)

Maroun Kassab , IBM Microelectronics, Essex Junction, VT
Leendert M. Huisman , IBM Microelectronics, Essex Junction, VT
Leah Pastel , IBM Microelectronics, Essex Junction, VT
pp. 661-668

Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor (Abstract)

Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
Ajay Ojha , Intel Corporation, Hillsboro, OR
M. Enamul Amyeen , Intel Corporation, Hillsboro, OR
Sangbong Lee , Intel Corporation, Hillsboro, OR
pp. 669-678
SESSION 24: LECTURE SERIES - TEST TRENDS AND CHALLENGES

Trends in manufacturing test methods and their implications (Abstract)

Sandip Kundu , Design Technology, Intel Corporation
T. M. Mak , Design Technology, Intel Corporation
Rajesh Galivanche , Design Technology, Intel Corporation
pp. 679-687

Trends in Testing Integrated Circuits (Abstract)

Robert Van Rijsinge , Philips Semiconductors - ATO, Nijmegen, Netherlands
Erik Jan Marinissen , Philips Research Laboratories, Netherlands
Bart Vermeulen , Philips Research Laboratories, Netherlands
Bram Kruseman , Philips Research Laboratories, Netherlands
Camelia Hora , Philips Research Laboratories, Netherlands
pp. 688-697
SESSION 25: BOARD AND SYSTEM TEST: SYSTEM AND FIELD TEST

Simulation Based System Level Fault Insertion Using Co-verification Tools (Abstract)

Hien Chau , Cisco Systems Inc., San Jose CA
Anoosh Hosseini , Cisco Systems Inc., San Jose CA,
Bill Eklow , Cisco Systems Inc., San Jose CA,
Toai Vo , Cisco Systems Inc., San Jose CA
Shyam Pullela , Cisco Systems Inc., San Jose CA
Chi Khuong , Cisco Systems Inc., San Jose CA,
pp. 704-710

Testing and Remote Field Update of Distributed Base Stations in a Wireless Network (Abstract)

Paul J. Wheatley , Lucent Technologies, Holmdel, NJ
Ken L. Cheung , Lucent Technologies, Whippany, NJ
Chen-Huan Chiang , Lucent Technologies, Holmdel, NJ
Kenneth Y. Ho , Lucent Technologies, Whippany, NJ
pp. 711-718

IPV6 CONFORMANCE TESTING: THEORY AND PRACTICE (Abstract)

Zhongcheng Li , Chinese Academy of Sciences. Beijing, China
Yujun Zhang , Chinese Academy of Sciences. Beijing, China
pp. 719-727
SESSION 26: ATE FOR THE FASTEST DEVICES

A HIGH-THROUGHPUT 5 GBPS TIMING AND JITTER TEST MODULE FEATURING LOCALIZED PROCESSING (Abstract)

Antonio H. Chan , DFT MicroSystems Canada Inc.
Mohamed M. Hafed , DFT MicroSystems Canada Inc.
Sebastien Laberge , DFT MicroSystems Canada Inc.
Gordon W. Roberts , DFT MicroSystems Canada Inc.
Bardia Pishdad , DFT MicroSystems Canada Inc.
Geoffrey Duerden , DFT MicroSystems Canada Inc.
Clarence Tam , DFT MicroSystems Canada Inc.
pp. 728-737

Tester Architecture For The Source Synchronous Bus (Abstract)

Masashi Shimanouchi , Credence Inc Baytech Drive, San Jose, CA
Robert Jackson , Credence Inc Baytech Drive, San Jose, CA
Howard Maassen , Credence Inc Baytech Drive, San Jose, CA
A.T. Sivaram , Credence Inc Baytech Drive, San Jose, CA
pp. 738-747

Modular Extension of ATE to 5 Gbps (Abstract)

D.C. Keezer , Georgia Institute of Technology
D. Minier , IBM Canada
F. Binette , IBM Canada
pp. 748-757
SESSION 27: SOC: MIXED SIGNALS, SIZE AND SPEED

Test Strategies For a 40Gbps Framer SoC (Abstract)

Jitendra B. Khare , Ample Communications Inc. Sacramento, CA
Hans T. Heineken , Ample Communications Inc. Sacramento, CA
pp. 758-763

DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI?s TNETD7300 ADSL Modem Device (Abstract)

Rubin A. Parekhji , Texas Instruments Pvt. Ltd., Bangalore, India
K. Nikila , Texas Instruments Pvt. Ltd., Bangalore, India
pp. 773-782
SESSION 28: RF TESTING

Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis (Abstract)

Erkan Acar , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
pp. 783-792

RF TESTING ON A MIXED SIGNAL TESTER (Abstract)

Jayendra Bhagat , IBM Corporation Essex Junction, VT, USA
Randy Wolf , IBM Corporation Essex Junction, VT, USA
Dana Brown , IBM Corporation Essex Junction, VT, USA
Jing Li , IBM Corporation Essex Junction, VT, USA
John Ferrario , IBM Corporation Essex Junction, VT, USA
pp. 793-800

Use of Embedded Sensors for Built-In-Test of RF Circuits (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Soumendu Bhattacharya , Georgia Institute of Technology, Atlanta, GA
pp. 801-809
ESSION 29: STATE SPACE EXPLORATION AND TEST GENERATION

Formal Verification of a System-on-Chip Using Computation Slicing (Abstract)

Vijay K. Garg , The University of Texas at Austin
Jayanta Bhadra , Motorola Inc.
Jacob A. Abraham , The University of Texas at Austin
Alper Sen , The University of Texas at Austin
pp. 810-819

State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation (PDF)

Qingwei Wu , Virginia Tech, Blacksburg, VA
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 820-829

Verification on Port Connections (Abstract)

Geeng-Wei Lee , National Chiao Tung University, Hsinchu, Taiwan
Jing-Yang Jou , National Chiao Tung University, Hsinchu, Taiwan
Chun-Yao Wang , National Chiao Tung University, Hsinchu, Taiwan
Juinn-Dar Huang , National Chiao Tung University, Hsinchu, Taiwan
pp. 830-836
SESSION 30: SOC TEST CASE STUDIES

Built-In Self-Test for System-on-Chip: A Case Study (Abstract)

John Sunwoo , Auburn University, Alabama USA
Charles Stroud , Auburn University, Alabama USA
Srinivas Garimella , Auburn University, Alabama USA
Jonathan Harris , Auburn University, Alabama USA
pp. 837-846

Hierarchical DFT Methodology - A Case Study (Abstract)

Richard Fisette , Mentor Graphics Corporation, Waltham, MA
Jeff Remmers , Plexus Design Solutions, Inc., Sudbury, MA
Moe Villalba , Plexus Design Solutions, Inc., Sudbury, MA
pp. 847-856
SESSION 31: BOARD AND SYSTEM TEST: BOARD AND SYSTEM-LEVEL BIST TECHNIQUES

A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems (Abstract)

Mike Ricchetti , ATI Research, Inc., Marlborough, MA
CJ Clark , Intellitech Corporation, Durham, NH
pp. 857-866

Towards Microagent based DBIST/DBISR (Abstract)

Alfredo Benso , Politecnico di Torino, Italy
Paolo Prinetto , Politecnico di Torino, Italy
Szilard Enyedi , Department of Automation , Technical University of Cluj-Napoca, Romania
Gavril Toderean , Department of Telecommunications,Technical University of Cluj-Napoca, Romania
Liviu Miclea , Department of Automation , Technical University of Cluj-Napoca, Romania
pp. 867-874

EMBEDDED TEST FOR A NEW MEMORY-CARD ARCHITECTURE (Abstract)

David Resnick , Cray Inc., Chippewa Falls, WI
pp. 875-882
SESSION 32: TEST OF DIGITAL, ANALOG AND MEMS C

Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Fei Su , Duke University, Durham, NC
pp. 883-892

TESTING THE CONFIGURABLE ANALOG BLOCKS OF FIELD PROGRAMMABLE ANALOG ARRAYS (Abstract)

M. Lubaszewski , IMSE-CNM Inst. de Microelectr. De Sevilla Sevilla, Spain
F. Azais , Universite de Montpellier II Montpellier Cedex 5, France
A. Jr. Andrade , DELET-UFRGS, Univ. Fed. do Rio Grande do Sul Porto Alegre, Brazil
T. Balen , DELET-UFRGS, Univ. Fed. do Rio Grande do Sul Porto Alegre, Brazil
M. Renovell , Universite de Montpellier II Montpellier Cedex 5, France
pp. 893-902

I/O Self-Leakage Test (Abstract)

Tawfik Rahal-Arabi , Intel Corporation, Logic Technology Development, Hillsboro, OR
Greg Taylor , Intel Corporation, Logic Technology Development, Hillsboro, OR
Ali Muhtaroglu , Intel Corporation, Logic Technology Development, Hillsboro, OR
Benoit Provost , Intel Corporation, Logic Technology Development, Hillsboro, OR
pp. 903-906

Defect Coverage Analysis of Partitioned Testing (Abstract)

Eric W Savage , Intel Corporation, Santa Clara, USA
Sreejit Chakravarty , Intel Corporation, Santa Clara, USA
Eric N Tran , Intel Corporation, Santa Clara, USA
pp. 907-915
SESSION 33: TEST COMPRESSION

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction (Abstract)

Laung-Terng Wang , SynTest Technologies, Inc., Sunnyvale , CA
Xiaoqing Wen , Kyushu Institute of Technology, Japan
Fei-Sheng Hsu , SynTest Technologies, Inc., Taiwan
Shyh-Horng Lin , SynTest Technologies, Inc., Taiwan
Sen-Wei Tsai , SynTest Technologies, Inc., Taiwan
Shianling Wu , SynTest Technologies, Inc., Sunnyvale , CA
Khader S. Abdel-Hafez , SynTest Technologies, Inc., Sunnyvale , CA
Hiroshi Furukawa , NEC Micro Systems, Ltd., Japan
pp. 916-925

DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS (Abstract)

Sybille Hellebrand , University of Innsbruck, Austria
Christofer S. Tautermann , University of Innsbruck, Austria
Armin Wurtenberger , University of Innsbruck, Austria
pp. 926-935

Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion (Abstract)

Kedarnath J. Balakrishnan , University of Texas, Austin, TX
Nur A. Touba , University of Texas, Austin, TX
pp. 936-944

Test Cost Reduction Through A Reconfigurable Scan Architecture (Abstract)

Alex Orailoglu , University of California, San Diego
Baris Arslan , University of California, San Diego
pp. 945-952
SESSION 34: MIXED-SIGNAL TEST TECHNIQUES

CONTROLLED SINE WAVE FITTING FOR ADC TEST (Abstract)

S. Sattler , Infineon Technologies Munich, Germany
H. Mattes , Infineon Technologies Munich, Germany
Claus Dworski , Infineon Technologies, Villach, Austria
pp. 963-971

Precise Pulse Width Measurement in Write Pre-compensation Test (Abstract)

Hideo Okawara , Agilent Technologies International Japan, Ltd. Tokyo, Japan
pp. 972-979

Power Supply Ramping for Quasi-static Testing of PLLs (Abstract)

Martin Posch , Philips Semiconductors Gratkorn Austria
Manfred Koller , Philips Semiconductors Gratkorn Austria
Cristiano Cenci , Philips Research Labs, Netherlands
Thomas Burger , Philips Semiconductors Gratkorn Austria
Guido Gronthoud , Philips Research Labs, Netherlands
Jose Pineda de Gyvez , Philips Research Labs, Netherlands
pp. 980-987
SESSION 35: EMBEDDED MEMORIES BIST AND REPAIR

Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI (Abstract)

Katsutoshi Uehara , Enterprise Server Division, Hitachi Ltd.
Masatoshi Hasegawa , Micro Device Division, Hitachi Ltd.
Hideo Sawamoto , Enterprise Server Division, Hitachi Ltd.
Masaji Kume , Enterprise Server Division, Hitachi Ltd.
Toru Kobayashi , Micro Device Division, Hitachi Ltd.
Hideki Hayashi , Hitachi ULSI Systems Co. Ltd.
Minoru Itakura , Enterprise Server Division, Hitachi Ltd.
pp. 988-996

A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories (Abstract)

Robert C. Aitken , Artisan Components, Caspian Court Sunnyvale, CA, USA
pp. 997-1005

AN SRAM WEAK CELL FAULT MODEL AND A DFT TECHNIQUE WITH A PROGRAMMABLE DETECTION THRESHOLD (Abstract)

Manoj Sachdev , University of Waterloo, Waterloo, ON, Canada
Andrei Pavlov , University of Waterloo, Waterloo, ON, Canada
Jose Pineda de Gyvez , Philips Research Labs, Eindhoven, Netherlands
pp. 1006-1015

Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM (Abstract)

Hiroshi Ito , Toshiba Corporation, Kawasaki, Japan
Shuso Fujii , Toshiba Corporation, Kawasaki, Japan
Atsushi Nakayama , Toshiba Corporation, Kawasaki, Japan
Osamu Wada , Toshiba Corporation, Kawasaki, Japan
Toshimasa Namekawa , Toshiba Corporation, Kawasaki, Japan
pp. 1016-1023
SESSION 36: DELAY TESTING

TIMING-INDEPENDENT TESTING OF CROSSTALK IN THE PRESENCE OF DELAY PRODUCING DEFECTS USING SURROGATE FAULT MODELS (Abstract)

Melvin A. Breuer , University of Southern California, Los Angeles, CA
Shahdad Irajpour , University of Southern California, Los Angeles, CA
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
pp. 1024-1033

Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks (PDF)

Michael S. Hsiao , Virginia Tech, Blacksburg, VA.
Manan Syal , Virginia Tech, Blacksburg, VA.
Sreejit Chakravarty , Intel Architecture Group, Intel Corporation, Santa Clara, CA
pp. 1034-1043

Analysis of delay caused by bridging faults in RLC interconnects (Abstract)

Kartik Mohanram , Department of Electrical and Computer Engineering Rice University, Houston, TX
Quming Zhou , Department of Electrical and Computer Engineering Rice University, Houston, TX
pp. 1044-1052

ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM (PDF)

Puneet Gupta , Cadence Design Systems, TDA, Endicott, NY
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 1053-1060
SESSION 37: APPLICATION SERIES - BOARD AND SYSTEM-LEVEL DFT AND TEST

A Hierarchical DFT Architecture for Chip, Board and System Test/Debug (Abstract)

Charles A. Njinda , Procket Networks, Cadillac Court, Milpitas, CA
pp. 1061-1071

"Real Life" System Testing of Networking Equipment (Abstract)

Sunil Kalidindi , IXIA Corporation., Calabasas CA,
Nghia Huynh , Cisco Systems Inc., San Jose CA,
Bill Eklow , Cisco Systems Inc., San Jose CA
Josh Goldstein , IXIA Corporation, Calabasas CA
pp. 1072-1077

Practical Instrumentation Integration Considerations (Abstract)

Thomas J. Anderson , Wavecrest Corporatio, Technology Drive, San Jose, CA
pp. 1078-1080
SESSION 38: FORMALIZING AND SIMULATING ATE

FORMAL DESCRIPTION OF TEST SPECIFICATION AND ATE ARCHITECTURE FOR MIXED-SIGNAL TEST (Abstract)

Baolin Deng , University of Erlangen-Nuremberg, Germany
Wolfram Glauert , University of Erlangen-Nuremberg, Germany
pp. 1081-1090

How to Bridge the Gap Between Simulationand Test (Abstract)

W. Ecker , Infineon Technologies AG, Munich, Germany
M. Zambaldi , Infineon Technologies AG, Munich, Germany
pp. 1091-1099

SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS (Abstract)

R Raghuraman , Texas Instruments Ltd., Bangalore , India.
pp. 1100-1107
SESSION 39: TESTING FOR SPEED - NEW AND PRACTICAL METHODS

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs (Abstract)

Manoj Sachdev , University of Waterloo, Waterloo, ON, Canada
Bhaskar Chatterjee , University of Waterloo, Waterloo, ON, Canada
Ali Keshavarzi , Circuits Research, Intel Labs Hillsboro, OR, USA
pp. 1108-1117

Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing (Abstract)

Ramyanshu Datta , University of Texas at Austin Austin, TX
Ravi Gupta , University of Texas at Austin Austin, TX
Manuel d'Abreu , Sun Microsystems, Sunnyvale, CA
Antony Sebastine , University of Texas at Austin Austin, TX
Jacob A. Abraham , University of Texas at Austin Austin, TX
pp. 1118-1127

SPEED CLUSTERING OF INTEGRATED CIRCUITS (Abstract)

Kenneth A. Brand , Stanford University, Stanford, CA, USA
Erik Volkerink , Stanford University, Stanford, CA, USA
Subhasish Mitra , Intel Corporation, Folsom, CA, USA
Edward J. McCluskey , Stanford University, Stanford, CA, USA
pp. 1128-1137
SESSION 40: PICOSECOND JITTER TESTING

BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics (Abstract)

Dongwoo Hong , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Chee-Kian Ong , University of California, Santa Barbara
pp. 1138-1147

A HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTER AND CALIBRATION SCHEME (Abstract)

Peter M. Levine , McGill University, Canada
Gordon W. Roberts , McGill University, Canada
pp. 1148-1157

Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications (Abstract)

Andy Martwick , Intel, Folsom, CA
Mike Li , Wavecrest, Technology Dr., San Jose, CA
Jan Wilstrup , Teradyne Inc., Fridley, MN
Gerry Talbot , AMD, MA
pp. 1158-1167
SESSION 41: APPLICATION SERIES - WAFER PROBE TECHNOLOGY

THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY (Abstract)

Jerry J. Broz , SWTW Technical Chair and International Test Solutions, Reno, NV
William R. Mann , SWTW General Chair and Rockwell International, Newport Beach, CA
Frederick L. Taber , BiTS Workshop General Chair and IBM Microelectronics, LaGrangeville, NY
Philip W. Seitzer , Distinguished Member of Technical Staff, Agere Systems, Allentown PA
pp. 1168-1195
SESSION 42: WRAPPERS AND MORE

Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores (Abstract)

Nicola Nicolici , McMaster University, Hamilton, ON
Qiang Xu , McMaster University, Hamilton, ON
pp. 1196-1202

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores (Abstract)

Sandeep Kumar Goel , Philips Research, Netherlands
Erik Jan Marinissen , Philips Research, Netherlands
Krishnendu Chakrabarty , Duke University
Anuja Sehgal , Duke University
pp. 1203-1212

An SOC Test Integration Platform and Its Industrial Realization (Abstract)

Chih-Tsun Huang , National Tsing Hua University, Taiwan
Kuo-Liang Cheng , National Tsing Hua University, Taiwan
Chih-Wea Wang , National Tsing Hua University, Taiwan
Jye-Yuan Lee , Global UniChip Corp., Taiwan
Shin-Wei Hung , Global UniChip Corp., Taiwan
Chih-Yen Lo , National Tsing Hua University, Taiwan
Jing-Reng Huang , National Tsing Hua University, Taiwan
Li-Ming Denq , National Tsing Hua University, Taiwan
pp. 1213-1222
SESSION 43: DESIGN-FOR-AVAILABILITY

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing (Abstract)

TM Mak , Intel Corp., Santa Clara (CA)
C. Metra , DEIS - U. of Bologna (Italy)
M. Omana , DEIS - U. of Bologna (Italy)
pp. 1223-1231

Architectures of Increased Availability Wireless Sensor Network Nodes (Abstract)

Jean-Samuel Chenard , McGill University, Canada
Zeljko Zilic , McGill University, Canada
Man Wah Chiang , McGill University, Canada
Katarzyna Radecka , Concordia University, Canada
pp. 1232-1241

Low Cost Concurrent Error Detection for the Advanced Encryption Standard (Abstract)

Ramesh Karri , Polytechnic University, Brooklyn, NY
Kaijie Wu , Polytechnic University, Brooklyn, NY
Michael Goessel , University of Potsdam, Germany
Grigori Kuznetsov , University of Potsdam, Germany
pp. 1242-1248
SESSION 44: ADVANCES IN TESTER ARCHITECTURE

Digital Synchronization for Reconfigurable ATE (Abstract)

Burnell G. West , Credence, Baytech Drive, San Jose, CA
Michael F. Jones , Credence, Baytech Drive, San Jose, CA
pp. 1249-1254

34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System (Abstract)

Masakatsu Suda , ADVANTEST Corporation, Japan
Daisuke Watanabe , ADVANTEST Corporation, Japan
Toshiyuki Okayasu , ADVANTEST Corporation, Japan
pp. 1255-1262

System Monitor for Diagnostic, Calibration and System Configuration (Abstract)

Miguel Conde , Credence Systems Corporation, Cedex - France
Michael Jones , Credence Systems Corporation, San Jose, CA
Russell Poffenberger , Credence Systems Corporation, San Jose, CA
Maurizio Gavardoni , Credence Systems Corporation, San Jose, CA
pp. 1263-1268
SESSION 45: ADVANCES IN DELAY TESTING

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits (Abstract)

Cassondra Neau , Purdue University
Bipul C Paul , Purdue University
Kaushik Roy , Purdue University
pp. 1269-1275

WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW: ANEW TYPE OF DELAY-FAULT MECHANISM (Abstract)

A. Keshavarzi , Circuit Research Labs., Intel Corporation, Portland, OR, USA
S.A. Bota , Univ. de les Illes Balears, Palma de Mallorca, Spain
M. Rosales , Univ. de les Illes Balears, Palma de Mallorca, Spain
J.L. Rosello , Univ. de les Illes Balears, Palma de Mallorca, Spain
J. Segura , Univ. de les Illes Balears, Palma de Mallorca, Spain
pp. 1276-1284

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model (Abstract)

Prabhu Krishnamurthy , LSI Logic Corporation, Fort Collins, CO
Brady Benware , LSI Logic Corporation, Fort Collins, CO
Mark Kassab , Mentor Graphics Corporation
Cam Lu , LSI Logic Corporation, Fort Collins, CO
Robert Madge , LSI Logic Corporation, Fort Collins, CO
John Van Slyke , LSI Logic Corporation, Fort Collins, CO
Martin Keim , Mentor Graphics Corporation
Janusz Rajski , Mentor Graphics Corporation
pp. 1285-1294
SESSION 46: APPLICATION SERIES - JITTER IN TEST

Jitter Models and Measurement Methods for High-Speed Serial Interconnects (Abstract)

Andy Kuo , University of British Columbia
Touraj Farahmand , University of British Columbia
Sassan Tabatabaei , Guide Technology, Sunnyvale, CA
Nelson Ou , University of British Columbia
Andre Ivanov , University of British Columbia
pp. 1295-1302

Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE (Abstract)

Korbinian Stieglbauer , Infineon Technologies AG, Munich, Germany
Gert Hansel , Infineon Technologies AG, Munich, Germany
pp. 1303-1312

JITTER GENERATION AND MEASUREMENT FOR TEST OF MULTIGBPS SERIAL IO (Abstract)

Michael Lee , Guide Technology, Sunnyvale, CA
Sassan Tabatabaei , Guide Technology, Sunnyvale, CA
Freddy Ben-Zeev , Guide Technology, Sunnyvale, CA
pp. 1313-1321
SESSION 47: ON-LINE TESTING AND FAULT TOLERANCE AT LOW COST

Reducing Power Consumption in Memory ECC Checkers (Abstract)

Nur A. Touba , Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
Sugato Basu , Dept. of Computer Sciences, University of Texas, Austin, TX
Shalini Ghosh , Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX
pp. 1322-1331

Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems (Abstract)

F. Corno , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
F. Esposito , FIAT Auto - Product and Process Engineering - Integrated Chassis Control - Torino, Italy
S. Tosato , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
M. Sonza Reorda , Politecnico di Torino - Dipartimento di Automatica e Informatica - Torino, Italy
pp. 1332-1339

On-line Testing Field Programmable Analog Array Circuits (Abstract)

Suchitra Kulkarni , Southern Illinois University Carbondale
Haibo Wang , Southern Illinois University Carbondale
Spyros Tragoudas , Southern Illinois University Carbondale
pp. 1340-1348
SESSION 48: ADVANCES IN SOC TEST

Integrating Core Selection in the SOC Test Solution Design-Flow (Abstract)

Erik Larsson , Linkopings Universitet, Sweden
pp. 1349-1358

Autonomous Yet Deterministic Test of SOC Cores (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 1359-1368

Test Scheduling for Network-on-Chip with BIST and Precedence Constraints (Abstract)

Erika Cota , Universidade Federal do Rio Grande do Sul, Brazil
Hamid Sharif , University of Nebraska
Chunsheng Liu , University of Nebraska
D.K. Pradhan , University of Bristol, UK
pp. 1369-1378
SESSION 49: ADC TESTING

Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACs (Abstract)

Degang Chen , Iowa State University Ames, IA
Hanjun Jiang , Iowa State University Ames, IA
Beatriz Olleta , Iowa State University Ames, IA
Randall L. Geiger , Iowa State University Ames, IA
pp. 1379-1388

Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation (Abstract)

Hongjoong Shin , University of Texas at Austin, Austin, TX
Ji Hwan (Paul) Chun , University of Texas at Austin, Austin, TX
Jacob A. Abraham , University of Texas at Austin, Austin, TX
Hak-soo Yu , University of Texas at Austin, Austin, TX
pp. 1389-1397

A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent Sampling (Abstract)

Degang Chen , Iowa State University
Randy Geiger , Iowa State University
Zhongjun Yu , Iowa State University
pp. 1398-1407
PANEL 1: OPEN ARCHITECTURE ATE: REALITY OR DREAM?

The Critical Need For Open ATE Architecture (PDF)

Sergio M Perez , Advantest America, Inc.
pp. 1409

Open Architecture ATE: Prospects and Problems (PDF)

Dr. Burnell G. West , Credence Systems Corporation, San Jose, USA
pp. 1410
PANEL 2: SECURITY VS. TEST QUALITY: CAN WE ONLY HAVE ONE AT A TIME?

Electronic circuit comprising a secret sub-module (PDF)

Herve FLEURY , Philips Semiconductors, France
pp. 1412
PANEL 3: GLAMOROUS ANALOG TESTABILITY - WE ALREADY TEST THEM AND SHIP THEM... SO WHAT IS THE PROBLEM?
PANEL 4: 100 DPM IN NANOMETER TECHNOLOGY - IS IT ACHIEVABLE?

Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs (PDF)

Brady R. Benware , LSI Logic Corporation, Fort Collins, CO
pp. 1418

Test Strategies for Nanometer Technologies (PDF)

Sanjay Sengupta , Intel Corp. Santa Clara, CA, USA
pp. 1421

Testing in a high volume DSM Environment (PDF)

Tom Storey , BAE Systems Manassas, VA
pp. 1422
PANEL 5: WHAT DO YOU MEAN MY BOARD TEST STINKS?

What Do You Mean My Board Test Stinks? (PDF)

Bill Eklow , Cisco Systems, Inc.
pp. 1423

Functional Test Coverage Effectiveness on the Decline (PDF)

Jay J. Nejedlo , Intel Corporation at Hillsboro, OR
pp. 1424

To Test or To Inspect, What is the Coverage? (PDF)

Rob Jukna , Jabil Circuit Inc.- Advanced Manufacturing Technology
pp. 1425

Board Test Coverage Needs to be Standardized (PDF)

Kenneth P. Parker , Agilent Technologies Loveland, CO
pp. 1426

What do you mean my Board Test stinks? (PDF)

Michael J Smith , Teradyne Inc, North Reading, MA. USA
pp. 1427
PANEL 6: DUDE! WHERE?S MY DATA? - CRACKING OPEN THE HERMETICALLY SEALED TESTER

Dude! Where?s my data? - Cracking Open the Hermetically Sealed Tester (PDF)

Manu Rehani , LSI Logic Corporation, OR
Robert Daasch , Portland State University
pp. 1428
PANEL 7: COST OF TEST: TAKING CONTROL

Cost of Test - Taking Control (PDF)

Nilanjan Mukherjee , Mentor Graphics Corporation, Wilsonville, OR
pp. 1431
PANEL 8: IS "DESIGN-TO-PRODUCTION" THE ULTIMATE ANSWER FOR JITTER, NOISE, AND BER CHALLENGES FOR MULTI-GB/S ICS?

Loopback or not? (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
pp. 1434

Options for High-Volume Test of Multi-GB/s Ports (PDF)

John C. Johnson , Intel Corporation, Test Platform Architecture and Development
pp. 1435

A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals (PDF)

Jim Sproch , Synopsys Test Automation Products Group
pp. 1437
PANEL 9: DIAGNOSIS MEETS PHYSICAL FAILURE ANALYSIS: HOW LONG CAN WE SUCCEED?

Panel 9 - Diagnostics vs. Failure Analysis (PDF)

Thomas W. Bartenstein , Cadence Design Inc., Endicott, NY
pp. 1439

Global Failure Localization: We Have To, But on What and How? (PDF)

Edward I. Jr. Cole , Sandia National Laboratories Albuquerque, USA
pp. 1440
PANEL 10: INVESTMENT VS. YIELD RELATIONSHIP FOR MEMORIES IN SOC

Memory Yield Improvement - SoC Design Perspective (PDF)

Jitendra B. Khare , Ample Communications, Inc., Fremont, CA USA.
pp. 1445

Investment vs. Yield Relationship for Memories and IP in SOC (PDF)

Joseph A. Reynick , eSilicon Corporation, Allentown, Pennsylvania, USA
pp. 1446

Plan Ahead for Yield (PDF)

Jun Qian , Cisco Systems, Inc. San Jose, USA
pp. 1447
ITC 2003 BEST PAPER:

Elimination of Traditional Functional Testing of Interface Timings at Intel (Abstract)

Anne Meixner , Intel Corporation
Mike Tripp , Intel Corporation
T.M. Mak , Intel Corporation
pp. 1448-1456
Author Index

Author Inxdex (PDF)

pp. 1457
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