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2004 International Conferce on Test (2004)
Charlotte, NC, USA
Oct. 26, 2004 to Oct. 28, 2004
ISSN: 1089-3539
ISBN: 0-7803-8581-0
pp: 173-180
Hong-Shin Jun , Cisco Systems, Inc., Tasman Drive San Jose, CA
Sung S. Chung , Cisco Systems, Inc., Tasman Drive San Jose, CA
Sang H. Baeg , Cisco Systems, Inc., Tasman Drive San Jose, CA
ABSTRACT
<p>This paper presents a new methodology that removes JTAG bottlenecks in system interconnect test. JTAG test has a limitation by targeting only low-speed testing. But, the system interconnect test requires the test to be run at system clock speed through the cluster of the network and also needs to diagnose the skew and delay characteristics of the cluster.</p> <p>Resolving the synchronization issue between a highspeed pattern clock and TCK, the proposed technique enables high frequency interconnection testing, cluster testing, and delay testing. Experimental results with test vehicles show that the test technique can be used with complex interconnections including differential signal lines, AC coupling, latency, and optical signal interconnections.</p>
INDEX TERMS
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CITATION

S. S. Chung, S. H. Baeg and H. Jun, "Removing JTAG Bottlenecks in System Interconnect Test," 2004 International Conferce on Test(ITC), Charlotte, NC, USA, 2004, pp. 173-180.
doi:10.1109/ITC.2004.153
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