The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2003)
Charlotte, NC, USA
Sept. 30, 2003 to Oct. 2, 2003
ISSN: 1089-3539
ISBN: 0-7803-8107-6
TABLE OF CONTENTS

Author Index (PDF)

pp. 1333
Session 1: Plenary

Test Challenges of Nanometer Technology (PDF)

Janusz Rajski , Mentor Graphics Corporation
pp. 13
Session 2: Memory Testing And Diagnosis

EEPROM Memory: Threshold Voltage Built In Self Diagnosis (Abstract)

J. M. Portal , IMT - Technop?le de Ch?teau Gombert
D. N? , ST-Microelectronics
H. Aziza , IMT - Technop?le de Ch?teau Gombert; ST-Microelectronics
pp. 23

Fault Pattern Oriented Defect Diagnosis for Memories (Abstract)

Chih-Wea Wang , National Tsing Hua University
Yung-Fa Chou , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Hong-Tzer Yang , Spirox Co.
Jih-Nung Lee , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Frank Huang , Spirox Co.
pp. 29
Session 3: Jitter Testing Techniques for > GB/S TX/RX Links

Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements (Abstract)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Mani Soma , University of Washington, Seattle, WA
Hirobumi Musha , Advantest Corporation, Gunma, Japan
Makoto Kurosawa , Advantest Corporation, Gunma, Japan
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
pp. 58

CMOS Built-In Test Architecture for High-Speed Jitter Measurement (Abstract)

Jeff Huard , Tacoma Design Center, National Semiconductor, Federal Way, WA
Eddie Chan , University of Washington, Seattle, WA
Karen Taylor , University of Washington, Seattle, WA
Jim Braatz , Tacoma Design Center, National Semiconductor, Federal Way, WA
Mani Soma , University of Washington, Seattle, WA
Hosam Haggag , Santa Clara Design Center, National Semiconductor, Santa Clara, CA
Henry C. Lin , University of Washington, Seattle, WA
Alan Chong , University of Washington, Seattle, WA
pp. 67
Session 4: High Yield And Effective Testing And Burn-In

Relating Yield Models to Burn-In Fall-Out in Time (Abstract)

Thomas S. Barnett , IBM Microelectronics
Adit D. Singh , Auburn University
pp. 77

Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results (Abstract)

Yoshihito Nishizaki , Kawasaki Microelectronics, Inc.
Chiaki Matsumoto , Kawasaki Microelectronics, Inc.
Hiroyuki Nakamura , Kawasaki Microelectronics, Inc.
Osamu Nakayama , Kawasaki Microelectronics, Inc.
Toshimi Kobayashi , Kawasaki Microelectronics, Inc.
Yoshitaka Kimura , Kawasaki Microelectronics, Inc.
pp. 85

Burn-in Temperature Projections for Deep Sub-micron Technologies (Abstract)

Arman Vassighi , University of Waterloo, Canada
C.F. Hawkins , University of New Mexico, Albuquerque
Manoj Sachdev , University of Waterloo, Canada
Oleg Semenov , University of Waterloo, Canada
Ali Keshavarzi , Intel Corporation, Hillsboro, OR
pp. 95
Session 5: Crosstalk And Delay Test

HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk (Abstract)

Xiaoliang Bai , University of California, San Diego, CA
Angela Krstic , University of California, Santa Barbara, CA
Sujit Dey , University of California, San Diego, CA
pp. 112

Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk (Abstract)

Rahul Kundu , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 122
Session 6: Improving Design Validation Coverage

Fault Injection for Verifying Testability at the VHDL Level (Abstract)

S. R. Seward , University of Arkansas, Fayetteville
P. K. Lala , University of Arkansas, Fayetteville
pp. 131

Coverage-Directed Management and Optimization of Random Functional Verification (Abstract)

Amir Hekmatpour , IBM Microelectronics, Research Triangle Park, North Carolina
James Coulter , IBM Microelectronics, Research Triangle Park, North Carolina
pp. 148
Session 7: Lecture Series-Board And System Test: Is PXI The Future of Functional Board Test?

The PXI Modular Instrumentation Architecture (Abstract)

Tim Fountain , National Instruments, Austin, TX
Eric Starkloff , National Instruments, Austin, TX
Garth Black , National Instruments, Austin, TX
pp. 156
Session 8: Pushing The Envelope of ATE

Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober (Abstract)

J.S. Davis , Georgia Institute of Technology
O. Liboiron-Ladouceur , Columbia University
K. Bergman , Columbia University
D.C. Keezer , Georgia Institute of Technology
pp. 166

A Production-Oriented Multiplexing System for Testing above 2.5 Gbps (Abstract)

D. Minier , IBM Canada
M.C. Caron , IBM Canada
D.C. Keezer , Georgia Institute of Technology, Atlanta
pp. 191
Session 9: ADC Test

A New Methodology For ADC Test Flow Optimization (Abstract)

Y. Bertrand , University of Montpellier / CNRS, France
S. Bernard , University of Montpellier / CNRS, France
M. Comte , University of Montpellier / CNRS, France
F. Aza? , University of Montpellier / CNRS, France
M. Renovell , University of Montpellier / CNRS, France
pp. 201

Method of reducing contactor effect when testing high-precision ADCs (Abstract)

Carsten Wegener , University College Cork, Ireland
Tom O'Dwyer , Raheen Industrial Estate, Limerick, Ireland
Michael Peter Kennedy , University College Cork, Ireland
Gwenol? Maugard , Raheen Industrial Estate, Limerick, Ireland
pp. 210

Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs (Abstract)

Kumar Parthasarathy , Iowa State University, Ames
Turker Kuyel , Iowa State University, Ames
Randall L. Geiger , Texas Instruments Inc., Dallas
Le Jin , Texas Instruments Inc., Dallas
Degang Chen , Texas Instruments Inc., Dallas
pp. 218
Session 10: Advances in Testing And Analysis Methods

Optical and Electrical Testing of Latchup in I/O Interface Circuits (Abstract)

Mujahid Muhammad , IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Pia Sanda , IBM Systems Group, Poughkeepsie, NY
Robert Gauthier , IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
Moyra K. McManus , IBM T.J. Watson Research Center, Yorktown Heights, NY
Alan J. Weger , IBM T.J. Watson Research Center, Yorktown Heights, NY
Franco Stellari , IBM T.J. Watson Research Center, Yorktown Heights, NY
Peilin Song , IBM T.J. Watson Research Center, Yorktown Heights, NY
Kiran Chatty , IBM Microelectronics Semiconductor and Research Development Center, Essex Junction, VT
pp. 236

Designed -in-diagnostics: A new optical method (Abstract)

K. R. Wilsher , NPTest, San Jose, CA
pp. 246

Fault Localization using Time Resolved Photon Emission and STIL Waveforms (Abstract)

Ketan Shah , NPTest, San Jose, CA
Philippe Perdu , CNES- French Space Agency, France
Romain Desplats , CNES- French Space Agency, France
Felix Beaudoin , CNES- French Space Agency, France
Nagamani Nataraj , NPTest, San Jose, CA
Ted Lundquist , NPTest, San Jose, CA
pp. 254
Session 11: Novel ATPG Approaches

Fault Collapsing via Functional Dominance (Abstract)

A. V. S. S. Prasad , Agere Systems, Bangalore, India
Vishwani D. Agrawal , Rutgers University, Piscataway, NJ
Madhusudan V. Atre , Agere Systems, Bangalore, India
pp. 274

Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal (PDF)

Qingwei Wu , Virginia Tech, Blacksburg, VA
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 281

Efficient Sequential ATPG for Functional RTL Circuits (PDF)

Michael Hsiao , Virginia Tech, Blacksburg, VA
Liang Zhang , Virginia Tech, Blacksburg, VA
Indradeep Ghosh , Fujitsu Labs. of America Inc., Sunnyvale, CA
pp. 290
Session 12: Advances in Diagnostics

Progressive Bridge Identification (Abstract)

Thomas J. Vogels , Carnegie Mellon University, Pittsburgh, PA
Wojciech Maly , Carnegie Mellon University, Pittsburgh, PA
R.D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
pp. 309

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault (Abstract)

Yu-Ting Hung , Faraday Technology Corporation
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR
Cheng-Ju Hsieh , Faraday Technology Corporation
Sudhakar M. Reddy , University of Iowa, Iowa City
Yu Huang , Mentor Graphics Corporation, Wilsonville, OR
pp. 319

An Efficient and Effective Methodology on the Multiple Fault Diagnosis (Abstract)

Kun-Han Tsai , Mentor Graphics Corporation
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Janusz Rajski , Mentor Graphics Corporation
Zhiyuan Wang , University of California, Santa Barbara
pp. 329
Session 13: Board And System Test: Advanced Applications of Boundary-Scan

A New Maximal Diagnosis Algorithm for Bus-structured Systems (Abstract)

YongSeung Shin , Yonsei University
Sunghoon Chun , Yonsei University
Sungho Kang , Yonsei University
DongSub Song , Yonsei University
YongJoon Kim , Yonsei University
pp. 349

A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic (Abstract)

Gary Kunselman , IBM Microelectronics - DFTS Development and Methodology - Burlington, VT
Paul Setlak , Cadence Design Systems - Test Design Automation - Endicott, NY
Hina Arora , Cadence Design Systems - Test Design Automation - Endicott, NY
Shazia Mardhani , Sun Microsystems - High End Server Engineering - Burlington, MA
Kevin Melocco , Cadence Design Systems - Test Design Automation - Endicott, NY
pp. 358

Optimal Interconnect ATPG Under a Ground-Bounce Constraint (Abstract)

Henk D.L. Hollmann , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
Erik Jan Marinissen , Philips Research Laboratories
pp. 369
Session 14: Embedded Memory BIST and Repair

Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores (Abstract)

P. Bernardi , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
A. Fudoli , ST Microelectronics, Cornaredo, Italy
D. Appello , ST Microelectronics, Cornaredo, Italy
M. Violante , Politecnico di Torino, Italy
V. Tancorre , ST Microelectronics, Cornaredo, Italy
pp. 379

BIST for Deep Submicron ASIC Memories with High Performance Application (Abstract)

Theo J. Powell , Texas Instruments Inc.
Wu-Tung Cheng , Mentor Graphics Corporation
Joseph Rayhawk , Mentor Graphics Corporation
Sherry Lai , Texas Instruments Inc.
Omer Samman , Mentor Graphics Corporation
Paul Policke , Texas Instruments Inc.
pp. 386

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Jin-Fu Li , National Central University
Archer Hsu , ADMTek Incorporated
Jen-Chieh Yeh , National Tsing Hua University
Peir-Yuan Tsai , ADMTek Incorporated
Rei-Fu Huang , National Tsing Hua University
Eugene Chow , ADMTek Incorporated
pp. 393
Session 15: Interface Magic

Automatic Diagnostic Program Generation for Mixed Signal Load Board (Abstract)

Kranthi K. Pinjala , Arizona State University
Bruce C. Kim , Arizona State University
Pramod Variyam , Texas Instruments, Inc.
pp. 403
Session 16: Test And Verification For Cores And SOCS

Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Tetsuo Uchiyama , SOC Design Center, CANON INC.
Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
pp. 415

Extraction Error Diagnosis and Correction in High-Performance Designs (Abstract)

Andreas Veneris , University of Toronto, ON
Paul Thadikaran , Intel Corporation, OR
J. Brandon Liu , University of Toronto, ON
Yu-Shen Yang , University of Toronto, ON
pp. 423

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores (Abstract)

A. Paschalis , University of Athens, Greece
D. Gizopoulos , University of Piraeus, Greece
Y. Zorian , Virage Logic, Fremont, CA
G. Xenoulis , University of Piraeus, Greece
N. Kranitis , University of Athens, Greece
pp. 431
Session 17: Keep Compressing This Test Data!

A Hybrid Coding Strategy For Optimized Test Data Compression (Abstract)

Sybille Hellebrand , University of Innsbruck, Austria
Armin W?rtenberger , University of Innsbruck, Austria
Christofer S. Tautermann , University of Innsbruck, Austria
pp. 451

Deterministic BIST Based on a Reconfigurable Interconnection Network (Abstract)

Lei Li , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
pp. 460
Session 18: Low-Power Scan

Double-Tree Scan: A Novel Low-Power Scan-Path Architecture (Abstract)

Sheng Zhang , University of Nebraska-Lincoln
Sharad C. Seth , University of Nebraska-Lincoln
Bhargab B. Bhattacharya , Indian Statistical Institute
pp. 470

A New Approach for Low Power Scan Testing (Abstract)

Masafumi Watati , Matsushita Electric Industrial Co., Ltd.
Takaki Yoshida , Matsushita Electric Industrial Co., Ltd.
pp. 480

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint (Abstract)

L. Guiller , Synopsys Inc., Mountain View, CA
C. Landrault , LIRMM, Universit? Montpellier II/CNRS, France
P. Girard , LIRMM, Universit? Montpellier II/CNRS, France
Y. Bonhomme , LIRMM, Universit? Montpellier II/CNRS, France
S. Pravossoudovitch , LIRMM, Universit? Montpellier II/CNRS, France
pp. 488
Session 19: Lecture Series-Board And System Test: IEEE 1149.6-A Practical Perspective

IEEE 1149.6 - A Practical Perspective (Abstract)

Mike Ricchetti , Intellitech, Durham, NH
Bill Eklow , Cisco Systems Inc., San Jose CA
Carl Barnhart , Cadence Design Systems, Ojai, CA
Terry Borroz , Teradyne, North Reading, MA
pp. 494
Session 20: Extremely Low-Cost Testers

Key Impediments to DFT-Focused Test and How to Overcome Them (Abstract)

Ken Posse , Teseda, Corporation
Geir Eide , Teseda, Corporation
pp. 503
Session 21: Application Series-Developing Test Interfaces

A Generic Test Path and DUT Model for DataCom ATE (Abstract)

Mike Li , Wavecrest Corporation, San Jose, CA
Jie Sun , Wavecrest Corporation, San Jose, CA
pp. 528
Session 22: Practical Application of I<sub>DDQ</sub>

Test Vector Generation Based on Correlation Model for Ratio-Iddq (Abstract)

Larry Kinney , University of Minnesota, Minneapolis
Xiaoyun Sun , University of Minnesota, Minneapolis
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 545

Hysteresis of Intrinsic IDDQ Currents (Abstract)

Nobuyuki Furukawa , Sony Semicon Kyushu Corp.
Yukio Okuda , Platform Technology Center, Sony Corp.
pp. 555

Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ (Abstract)

K. Cota , LSI Logic Corporation, Gresham, Oregon
R. Daasch , Portland State University, Oregon
C. Schuermyer , LSI Logic Corporation, Gresham, Oregon
R. Madge , LSI Logic Corporation, Gresham, Oregon
B. Benware , LSI Logic Corporation, Gresham, Oregon
L. Ning , Portland State University, Oregon
pp. 565
Session 23: Delay Test

High Quality ATPG for Delay Defects (PDF)

Puneet Gupta , Virginia Tech, Blacksburg
Michael S. Hsiao , Virginia Tech, Blacksburg
pp. 584
Session 24: Optimizing Efficiency in SOC Testing

Modeling Scan Chain Modifications For Scan-in Test Power Minimization (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 602

Power-aware NoC Reuse on the Testing of Core-based Systems (Abstract)

Fl?vio Wagner , Universidade Federal do Rio Grande do Sul
?rika Cota , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
Marcelo Lubaszewski , Universidade Federal do Rio Grande do Sul
pp. 612

On Reducing Wrapper Boundary Register Cells in Modular SOC Testing (Abstract)

Nicola Nicolici , McMaster University, Hamilton, ON
Qiang Xu , McMaster University, Hamilton, ON
pp. 622
Session 25: Board And System Test: AC-Interconnect Board Test Techniques

First IC Validation of IEEE Std. 1149.6 (Abstract)

Suzette Vandivier , Agilent Technologies, Ft. Collins, CO.
Mark Wahl , Agilent Technologies, Ft. Collins, CO.
Jeff Rearick , Agilent Technologies, Ft. Collins, CO.
pp. 632

Design and Implementation of IEEE 1149.6 (PDF)

Ivan Duzevik , National Semiconductor, South Portland, Maine
pp. 640

Adapting JTAG for AC Interconnect Testing (Abstract)

Lee Whetsel , Texas Instruments
pp. 641
Session 26: RF Testing

VDD Ramp Testing for RF Circuits (Abstract)

Rashid Amine , Philips Research Laboratories
Jos? Pineda de Gyvez , Philips Research Laboratories
Guido Gronthoud , Philips Research Laboratories
pp. 651

Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models (Abstract)

Achintya Halder , Georgia Institute of Technology, Atlanta
Soumendu Bhattacharya , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 665
Session 27: Lecture Series-Introduction to MEMS

MEMS Design And Verification (Abstract)

Tamal Mukherjee , Carnegie Mellon University, Pittsburgh, PA
pp. 681

MEMS Fabrication (Abstract)

Gary K. Fedder , Carnegie Mellon University, Pittsburgh, PA
pp. 691
Session 28: Application of I<sub>DDX</sub>

Effectiveness Improvement of ECR Tests (Abstract)

Bob Robotka , Guidant Corporation
Wanli Jiang , Guidant Corporation
Eric Peterson , Guidant Corporation
pp. 699

Impedance Profile of a Commercial Power Grid and Test System (Abstract)

Dhruva Acharyya , University of Maryland, Baltimore County
Jim Plusquellic , University of Maryland, Baltimore County
pp. 709

CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing (Abstract)

A. Keshavarzi , Intel Corporation, Hillsboro, Oregon
B. Bloechel , Intel Corporation, Hillsboro, Oregon
J. Segura , Univ. de les Illes Balears, Dept. F?sica, Palma de Mallorca, Spain
B. Alorda , Intel Corporation, Hillsboro, Oregon
pp. 719
Session 29: Logic BIST

Convolutional Compaction of Test Responses (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa
Chen Wang , Mentor Graphics Corporation
Jerzy Tyszer , Poznan University of Technology
pp. 745
Session 30: Microprocessor Test

Latch Divergency In Microprocessor Failure Analysis (Abstract)

Paul Dickinson , Sun Microsystems, Inc.
Ishwar Parulkar , Sun Microsystems, Inc.
Peter Dahlgren , Sun Microsystems, Inc.
pp. 755
Session 31: Board And System Test: Advances in Testing Microprocessor Motherboards

An extension to JTAG for at-speed debug on a system (Abstract)

Frank van der Heyden , Philips Research Eindhoven, The Netherlands
Tom Waayers , Philips Research Eindhoven, The Netherlands
Leon van de Logt , Philips Research Eindhoven, The Netherlands
pp. 785
Session 32: Latest Developments in ATE Software

Data Critically Estimation In Software Applications (Abstract)

G. Di Natale , Politecnico di Torino, Italy
A. Benso , Politecnico di Torino, Italy
S. Di Carlo , Politecnico di Torino, Italy
L. Tagliaferri , Politecnico di Torino, Italy
P. Prinetto , Politecnico di Torino, Italy
pp. 802

Case Study - Using STIL as Test Pattern Language (Abstract)

Rusty Carruth , NPTest, Inc. LLC
Steve Roehling , NPTest, Inc. LLC
Daniel Fan , NPTest, Inc. LLC
pp. 811

Outlier Detection for DPPM Reduction (Abstract)

Paul Buxton , The Alba Centre, The Alba Campus, Livingston, Scotland
Paul Tabor , Test Advantage Inc, Tempe, AZ
pp. 818
Session 33: Lecture Series-MEMS Testing

Failure Mechanisms in MEMS (Abstract)

Jeremy A. Walraven , Sandia National Laboratories, Albuquerque, NM
pp. 828

Tools and Techniques for Failure Analysis and Qualification of MEMS (Abstract)

Jeremy A. Walraven , Sandia National Laboratories, Albuquerque, NM
pp. 834

MEMS Manufacturing Testing: An Accelerometer Case Study (Abstract)

Dennis Stanerson , Motorola, Tempe, AZ
Theresa Maudie , Motorola, Tempe, AZ
Ron Bieschke , Motorola, Tempe, AZ
Alex Hardt , Motorola, Tempe, AZ
Mike Miller , Motorola, Tempe, AZ
Rick Nielsen , Motorola, Tempe, AZ
pp. 843

Future Challenges for MEMS Failure Analysis (Abstract)

Jeremy A. Walraven , Sandia National Laboratories, Albuquerque, NM
pp. 850
Session 34: Failure Mechanisms And Test Solutions For DSM ICS

Deformations of IC Structure in Test and Yield Learning (Abstract)

T. Vogels , Carnegie Mellon University, Pittsburgh, PA
R. D. Blanton , Carnegie Mellon University, Pittsburgh, PA
W. Maly , Carnegie Mellon University, Pittsburgh, PA
T. Storey , PDF Solutions
T. Zanon , Carnegie Mellon University, Pittsburgh, PA
pp. 856

Detection of Resistive Shorts in Deep Sub-micron Technologies (Abstract)

Stefan van den Oetelaar , Philips Research Laboratories
Bram Kruseman , Philips Research Laboratories
pp. 866

Analyzing the Effectiveness of Multiple-Detect Test Sets (Abstract)

R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
Kumar N. Dwarakanath , Carnegie Mellon University, Pittsburgh, PA
Anirudh B. Shah , Carnegie Mellon University, Pittsburgh, PA
pp. 876

Novel Transient Fault Hardened Static Latch (Abstract)

Cecilia Metra , D.E.I.S. University of Bologna, Italy
Martin Oma? , D.E.I.S. University of Bologna, Italy
Daniele Rossi , D.E.I.S. University of Bologna, Italy
pp. 886
Session 35: Can Concurrent Detection Be Achieved At Low Cost?

Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits (Abstract)

Kartik Mohanram , University of Texas at Austin, TX
Nur A. Touba , University of Texas at Austin, TX
pp. 893

On-line Detection of Faults in Carry-Select Adders (Abstract)

P. K. Lala , University of Arkansas, Fayetteville
B. Kiran Kumar , University of Arkansas, Fayetteville
pp. 912

Parity-Based Concurrent Error Detection in Symmetric Block Ciphers (Abstract)

Grigori Kuznetsov , University of Potsdam
Michael Goessel , University of Potsdam
Ramesh Karri , Polytechnic University
pp. 919
Session 36: Test Economics

Hybrid Multisite Testing at Manufacturing (Abstract)

F. J. Meyer , Northeastern University, Boston, Mass
F. Karimi , LTX Corp., San Jose, CA
F. Lombardi , Northeastern University, Boston, Mass
H. Hashempour , Northeastern University, Boston, Mass
pp. 927
Session 37: Board And System Test: Testing Multiboard Systems

Agent Based DBIST/DBISR And Its Web/Wireless Management (Abstract)

Alfredo Benso , Politecnico di Torino, Italy
Enyedi Szil?rd , Technical University of Cluj-Napoca, Romania
Liviu Miclea , Technical University of Cluj-Napoca, Romania
Paolo Prinetto , Politecnico di Torino, Italy
Gavril Toderean , Technical University of Cluj-Napoca, Romania
pp. 952

Instruction Based BIST for Board/System Level Test of External Memories and Internconnects (Abstract)

Ismet Bayraktaroglu , Sun Microsystems, Sunnyvale, CA
John Bell , Sun Microsystems, Sunnyvale, CA
Olivier Caty , Sun Microsystems, Sunnyvale, CA
Amitava Majumdar , Sun Microsystems, Sunnyvale, CA
Richard Lee , Microsoft Corporation, Mountain View, CA
Lisa Curhan , Sun Microsystems, Sunnyvale, CA
pp. 961

Test-Based Model Generation For Legacy Systems (Abstract)

Bernhard Steffen , University of Dortmund, Germany
Hardi Hungar , University of Dortmund, Germany; METAFrame Technologies GmbH, Germany
Tiziana Margaria , University of Dortmund, Germany; METAFrame Technologies GmbH, Germany
pp. 971

Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices (Abstract)

Kenneth L. Williams , Texas Instruments, Inc. Sherman, Texas
Rakesh N. Joshi , Texas Instruments, Inc. Sherman, Texas
Lee Whetsel , Texas Instruments, Inc. Sherman, Texas
pp. 981
Session 38: Lecture Series-P1500 Mergeable Cores

Overview of the IEEE P1500 Standard (Abstract)

Rohit Kapur , Synopsys, Inc., Mountain View, CA
Karim Arabi , PMC Sierra, Burnaby, BC
Lee Whetsel , Texas Instruments, Dallas, TX
Yervant Zorian , Virage Logic, Fremont, CA
Francisco DaSilva , Synopsys, Inc., Mountain View, CA
pp. 988

The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data (Abstract)

Pradipta Ghosh , Sun Microsystems
Sudipta Bhawmik , Agere Systems
Scott Davidson , Sun Microsystems
Kamran Zarrineh , Sun Microsystems
Michael G. Wahl , Universit?t Siegen
pp. 998
Session 39: I/O Testing-Probe or Not?

Low Contact-Force Fritting Probe Card Using Buckling Microcantilevers (Abstract)

Toshihiro Itoh , University of Tokyo
Tadatomo Suga , University of Tokyo
Kenichi Kataoka , University of Tokyo
pp. 1008

Elimination of Traditional Functional Testing of Interface Timings at Intel (Abstract)

T.M. Mak , Intel Corporation
Anne Meixner , Intel Corporation
Mike Tripp , Intel Corporation
pp. 1014

A BIST Solution for The Test of I/O Speed (Abstract)

Cheng Jia , Georgia Institute of Technology, Atlanta
Linda Milor , Georgia Institute of Technology, Atlanta
pp. 1023
Session 40: Quality

Impact of Multiple-Detect Test Patterns on Product Quality (Abstract)

Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Prabhu Krishnamurthy , LSI Logic Corporation, Gresham, OR
Sreenevasan Ranganathan , LSI Logic Corporation, Gresham, OR
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Nagesh Tamarapalli , Mentor Graphics Corporation, Wilsonville, OR
Robert Madge , LSI Logic Corporation, Gresham, OR
Chris Schuermyer , LSI Logic Corporation, Gresham, OR
Brady Benware , LSI Logic Corporation, Gresham, OR
pp. 1031

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects (Abstract)

T. W. Williams , Synopsys, Inc.
Angela Krstic , UC-Santa Barbara
M. Ray Mercer , Texas A&M U.
Kwang-Ting Cheng , UC-Santa Barbara
Leonard Lee , UC-Santa Barbara
Magdy S. Abadir , Motorola, Inc.
Li-C. Wang , UC-Santa Barbara
pp. 1041

Simulating Resistive Bridging and Stuck-At Faults (Abstract)

Ilia Polian , Albert-Ludwigs-University
Piet Engelke , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Michel Renovell , LIRMM - UMII
pp. 1051
Session 41: Test Data Compression

On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding (Abstract)

Sudhakar M. Reddy , University of Iowa, IA
Irith Pomeranz , Purdue University, W. Lafayette, IN
Sandip Kundu , Intel corp., Austin, TX
Masao Naruse , RENASAS, Technology corp., Kodaira-shi, Tokyo
pp. 1060

ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume (Abstract)

Domenico Chindamo , Agilent Technologies, Italy
Erik Volkerink , Agilent Technologies, Palo Alto, CA
Soenke Rogge , Philips Semiconductors, Germany
Harald Vranken , Philips Research, Digital Design & Test, The Netherlands
Friedrich Hapke , Philips Semiconductors, Germany
pp. 1069

On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs (Abstract)

Sudhakar M. Reddy , University of Iowa, IA
Huaxing Tang , University of Iowa, IA
Irith Pomeranz , Purdue University, West Lafayette, IN
pp. 1079
Session 42: At-Speed Testing-New Solutions to Old Problems

Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing (Abstract)

Kun Young Chung , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 1089

DFFT : Design For Functional Testability (Abstract)

Leon Xiao , Broadcom Corporation, Santa Clara, California
Haluk Konuk , Broadcom Corporation, Santa Clara, California
pp. 1105
Session 43: Extending IEEE 1149.1 Into The Backplane

Backplane Test Bus Applications For IEEE STD 1149.1 (Abstract)

Clayton Gibbs , Texas Instruments, Inc., Sherman, Texas
pp. 1115
Session 44: Infrastructure IP

Infrastructure IP for Back-End Yield Improvement (Abstract)

J. M. Portal , IMT - Technop?le de Ch?teau Gombert, France
B. Borot , ST-Microelectronics, France
L. Forli , IMT - Technop?le de Ch?teau Gombert, France; ST-Microelectronics, France
D. N? , ST-Microelectronics, France
pp. 1129

A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling (Abstract)

Zebo Peng , Link?pings Universitet, Sweden
Erik Larsson , Link?pings Universitet, Sweden
pp. 1135
Session 45: Analog Model-Based Testing

Analog Circuit Test using Transfer Function Coe .cient Estimates (Abstract)

Jacob Savir , New Jersey Institute of Technology
Zhen Guo , New Jersey Institute of Technology
pp. 1155

Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results (Abstract)

Sasi Cherubal , Ardext Technologies, Tucson, AZ
Thomas Kuehl , Texas Instruments Inc., Tucson, AZ
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
Bob Cometta , Texas Instruments Inc., Tucson, AZ
David Majernik , Arctic Systems Inc, Burtonsville, MD
Randy Newby , Texas Instruments Inc., Tucson, AZ
Ram Voorakaranam , Ardext Technologies, Tucson, AZ
pp. 1174
Session 46: Test of Future Integrated Systems

Towards Structural Testing of Superconductor Electronics (Abstract)

Hans G. Kerkhoff , University of Twente, The Netherlands
Arun A. Joseph , University of Twente, The Netherlands
pp. 1182

Testing of Droplet-Based Microelectrofluidic Systems (Abstract)

Sule Ozev , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
Fei Su , Duke University, Durham, NC
pp. 1192

Defect Tolerance at the End of the Roadmap (Abstract)

Mahim Mishra , Carnegie Mellon University, Pittsburgh, PA
Seth C. Goldstein , Carnegie Mellon University, Pittsburgh, PA
pp. 1201
Session 47: DFT Industrial Case Studies

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions (Abstract)

Nilanjan Mukherjee , Mentor Graphics Corporation, Wilsonville, OR
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR
Frank Poehl , Infineon Technologies AG, Munich, Germany
Nagesh Tamarapalli , Mentor Graphics Corporation, Wilsonville, OR
Matthias Beck , Infineon Technologies AG, Munich, Germany
Ralf Arnold , Infineon Technologies AG, Munich, Germany
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Peter Muhmenthaler , Mentor Graphics Corporation, Wilsonville, OR
pp. 1211

Circular BIST testing the digital logic within a high speed Serdes (Abstract)

Richard Simpson , Texas Instruments Ltd.
Graham Hetherington , Texas Instruments Ltd.
pp. 1221

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing (Abstract)

Pete Johnson , Intel Corporation
David M. Wu , Intel Corporation
Greg Parrish , Intel Corporation
Subhasish Mitra , Intel Corporation
Mike Lin , Intel Corporation
Anil Sabbavarapu , Intel Corporation
Dale March , Intel Corporation
Kee Sup Kim , Intel Corporation
Talal Jaber , Intel Corporation
pp. 1229
Session 48: Interconnect Testing And BIST For FPGAS

FPGA Interconnect Delay Fault Testing (Abstract)

Erik Chmelar , Stanford University
pp. 1239

Application of Built in Self-Test for Interconnect Testing of FPGAs (Abstract)

Dereck A. Fernandes , University of Massachusetts, Amherst
Ian G. Harris , University of California Irvine
pp. 1248

BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study (Abstract)

Keshia N. Leach , University of North Carolina at Charlotte
Charles E. Stroud , Auburn University, AL
Thomas A. Slaughter , University of North Carolina at Charlotte
pp. 1258
Session 49: Board And System Test: Other Aspects of Board Test

Board Test Coverage: The Value of Prediction and How to Compare Numbers (PDF)

Frans de Jong , Philips Research Laboratories, Eindhoven, NL
Wouter Rijckaert , Philips Research Laboratories, Eindhoven, NL
pp. 1277

IEEE P1581: To Live or Let die? (PDF)

Frans de Jong , Philips Research Eindhoven, NL
Leon van de Logt , Philips Research Eindhoven, NL
pp. 1278
Panel 1: How (In) Adequate is One-Time Testing?

Panel Synopsis - How (In)Adequate is One Time Testing? (PDF)

Rubin A. Parekhji , Texas Instruments (India) Pvt. Ltd., Murugeshpalya, Bangalore
pp. 1279

The Increasing Importance of On-line Testing to Ensure High-Reliability Products (PDF)

Phil Nigh , IBM Microelectronics, Essex Junction, Vermont
pp. 1281

How (In)Adequate is One-time Testing (PDF)

Peter Ehlig , Texas Instruments, Inc., Stafford, Texas
pp. 1283

Yield Threats and Inadequacy of One-time Test (PDF)

Yervant Zorian , Virage Logic Corporation, Fremont, California
pp. 1284
Panel 2: My DFT Is Better Than Yours... Is Better than None...
Panel 3: RF Test 101: Defining The Problem, Finding Solutions

Improving Wireless Product Testing: An Opportunity for University and Industry Collaboration (PDF)

Jim Paviol , Intersil Corporation-Wireless Division, Melbourne, FL
pp. 1289
Panel 4: The Confluence of Manufacturing Test And Design Validation

The Confluence of Manufacturing Test and Design Validation (PDF)

Franco Fummi , Universit? di Verona, Verona, Italy
pp. 1291

Design Verification Problems: Test To The Rescue? (PDF)

Prab Varma , Veritable Inc., Mountain View, CA
pp. 1292

The Confluence of Manufacturing Test and Design Validation (PDF)

Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 1293
Panel 5: PXI: A Solution For Board Functional Test?

PXI: A Solution For Board Functional Test? (PDF)

Jim Webster , Bae Systems, Edinburgh
pp. 1294

PXI - A New Architecture for Many Testing Requirements (PDF)

Bob Stasonis , Teradyne, Inc., North Reading, MA
pp. 1296
Panel 6: Future ATE: Perspectives And Requirements

Future ATE: Perspectives & Requirements (PDF)

Fidel Muradali , Agilent Technologies
pp. 1297

Future ATE: Perspectives & Requirements (PDF)

Lee Y. Song , Teradyne, Inc., Agoura Hills, CA
pp. 1300
Panel 7: Diagnosis In Modern Time-To-Volume-The Tip of The Iceberg

Debug and Diagnosis in the Age of System-on-a-Chip (PDF)

Robert Molyneaux , Sun Microsystems Inc., Austin, Texas
pp. 1303

Silicon Diagnosis (PDF)

Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, Oregon
pp. 1305
Panel 8: Multi-GB/S IC Test Challenges And Solutions

Managing the Multi-Gbit/s Test Challenges (PDF)

Bernd Laquai , Agilent Technologies, Boeblingen
Ulrich Schoettmer , Agilent Technologies, Boeblingen
pp. 1310

Jitter Test in Production for High Speed Serial Links (PDF)

Yi Cai , Agere Systems, Allentown, Pennsylvania
pp. 1312
Panel 9: DFM: The Real 90-NM Hurdle

DFM: The Real 90nm Hurdle (PDF)

Rob Aitken , Artisan Components, Sunnyvale, CA
pp. 1313

Silicon IP And Successful DFM (PDF)

Rob Aitken , Artisan Components, Sunnyvale, CA
pp. 1314

DFM - An Industry Paradigm Shift (PDF)

Cliff Ma , Anchor Semiconductor, Inc., Santa Clara, California
pp. 1315

Design for Manufacturability - or the meaning of 'subtle' (PDF)

Stefan Eichenberger , Philips Semiconductors, The Netherlands
pp. 1316

DFM - A Fabless Perspective (PDF)

Jitendra B. Khare , Ample Communications, Inc. Fremont, CA
pp. 1317
Panel 10: Testing 3G-Controlled Systems: A Time to Rejoice or A Time to Feel Pain?

Self-Testing and Self-Healing via Mobile Agents (PDF)

Alfredo Benso , Politecnico di Torino, Italy
pp. 1320
ITC 2002 Best Paper:

Architecting Millisecond Test Solutions for Wireless Phone RFIC's (Abstract)

John Ferrario , IBM RF & Analog Test Development, Essex Junction, Vt
Randy Wolf , IBM RF & Analog Test Development, Essex Junction, Vt
Steve Moss , IBM RF & Analog Test Development, Essex Junction, Vt
pp. 1325
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