The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2002)
Baltimore, MD, USA
Oct. 7, 2002 to Oct. 10, 2002
ISBN: 0-7803-7543-2
TABLE OF CONTENTS
Introduction

Author Index (PDF)

pp. 1249
EXECUTIVE PANEL: HOMEGROWN VERSUS COMMERCIAL SOLUTIONS FOR LOW-COST TEST
SPECIAL PANEL: TESTING THE TESTER

Testing The Tester (PDF)

Rochit Rajsuman , Advantest America R & D Center, Inc.
pp. 27

Testing The Tester (PDF)

Rochit Rajsuman , Advantest America R & D Center, Inc.
pp. 30
Keynote Address
Invited Address

The Heisenberg Uncertainty of Test (PDF)

Peter Maxwell , Agilent Technologies
pp. 13
SESSION 2: MEMORY TESTING

An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell (Abstract)

H. Aziza , ICF/L2MP-UMR CNRS and ST-Microelectronics
J. M. Portal , ICF/L2MP-UMR CNRS
L. Forli , ICF/L2MP-UMR CNRS and ST-Microelectronics
D. N? , ST-Microelectronics
pp. 31

Diagonal Test and Diagnostic Schemes for Flash Memories (Abstract)

Sau-Kwo Chiu , National Tsing Hua University
Jen-Chieh Yeh , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 37

Efficient Embedded Memory Testing with APG (Abstract)

A. Yiin , Intel Corporation
Daniel Fan , NPTest
A. T. Sivaram , NPTest
pp. 47
SESSION 3: ADVANCES IN SOC TESTING

IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips (Abstract)

Sjaak Bakker , Philips Semiconductors SLE
Tom Waayers , Philips Research Laboritories
Bart Vermeulen , Philips Research Laboritories
pp. 55

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation
Omer Samman , Mentor Graphics Corporation
Nilanjan Mukherjee , Mentor Graphics Corporation
Chien-Chung Tsai , Mentor Graphics Corporation
Paul Reuter , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa
Yu Huang , Mentor Graphics Corporation
Yahya Zaidan , Mentor Graphics Corporation
pp. 74
SESSION 4: DEFECT-ORIENTED TEST

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout (Abstract)

Kozo Kinoshita , Osaka Gakuin University
Seiji Kajihara , Kyushu Institute of Technology
Huaxing Tang , University of Iowa
Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
pp. 83

Parametric Failures in CMOS ICs — A Defect-Based Analysis (Abstract)

Charles Hawkins , University of New Mexico
Jerry Soden , Sandia National Labs
Ali Keshavarzi , Intel Corp
Jaume Segura , University of the Balearic Islands
pp. 90
SESSION 5: HIGH-PERFORMANCE TIMING MEASUREMENTS

Frequency/Phase Movement Analy i by Orthogonal Demodulation (Abstract)

Hideo Okawara , Agilent Technologies Japan, Ltd.
pp. 110

A Wavelet-Based Timing Parameter Extraction Method (Abstract)

Jessica Yan , University of Washington
Mani Soma , University of Washington
Welela Haileselassie , University of Washington
Rajesh Raina , Motorola Inc.
pp. 120

An Embedded Core for Sub-Picosecond Timing Measurements (Abstract)

Andr? Ivanov , University of British Columbia
Sassan Tabatabaei , Vector 12 Corp.
pp. 129
SESSION 6: TEST DATA REDUCTION

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume (Abstract)

J. Th. van der Linden , Scientificial, Delft
A. J. van de Goor , Delft University of Technology
M. J. Geuzebroek , Delft University of Technology
pp. 138

Packet-Based Input Test Data Compression Techniques (Abstract)

Ajay Khoche , Agilent Laboratories
Subhasish Mitra , Intel Corporation
Erik H. Volkerink , Stanford University and Agilent Laboratories
pp. 154
SESSION 7: MEMORY DFT,BIST AND REPAIR

DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs (Abstract)

N. Otsuka , Toshiba Corporation
K. Kushida , Toshiba Corporation
A. Tohata , Toshiba Microelectronics Corporation
O. Hirabayashi , Toshiba Corporation
A. Suzuki , Toshiba Corporation
Y. Takeyama , Toshiba Corporation
A. Kawasumi , Toshiba Corporation
T. Yabe , Toshiba Corporation
pp. 164

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test (Abstract)

T. Tada , Mitsubishi Electric Corporation
Kenji Gamo , Osaka University
Shigeki Tomishima , Mitsubishi Electric Corporation and Osaka University
Mitsutaka Niiro , Mitsubishi Electric Corporation
Masanao Maruta , Mitsubishi Electric Corporation
Hiroaki Tanizaki , Mitsubishi Electric Engineering Co., Ltd.
Hideto Hidaka , Mitsubishi Electric Corporation
pp. 170

Integration of SRAM Redundancy into Production Test (Abstract)

Juraj Povazanec , Infineon Technologies Asia Pacific Pte Ltd
Jayasanker Jayabalan , Infineon Technologies Asia Pacific Pte Ltd
pp. 187
SESSION 8: DESIGN VALIDATION — NOVEL ATPG APPLICATIONS

Verifying Properties Using Sequential ATPG (Abstract)

Jacob A. Abraham , University of Texas at Austin
Daniel G. Saab , Case Western Reserve University
Vivekananda M. Vedula , University of Texas at Austin
pp. 194

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems (Abstract)

Tao Feng , University of California at Santa Barbara
Madhu K. Iyer , University of California at Santa Barbara
Ganapathy Parthasarathy , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
Li-C. Wang , University of California at Santa Barbara
Magdy S. Abadir , Motorola
pp. 203

Design Rewiring Using ATPG (Abstract)

Mandana Amiri , University of Toronto
Andreas Veneris , University of Toronto
Magdy S. Abadir , Motorola
pp. 223
SESSION 9: NOVEL TECHNIQUES FOR DIAGNOSTICS

Fault Tuples in Diagnosis of Deep-Submicron Circuits (Abstract)

R. Desineni , Carnegie Mellon University
W. Maly , Carnegie Mellon University
T. J. Vogels , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
J. T. Chen , Carnegie Mellon University
K. N. Dwarakanath , Carnegie Mellon University
pp. 233

A Persistent Diagnostic Technique for Unstable Defects (Abstract)

Hiroki Yamanaka , Hitachi, Ltd.
Toshio Ikeda , Hitachi, Ltd.
Masahiro Takakura , Hitachi Engineering Co., Ltd.
Yasuo Sato , Hitachi, Ltd.
Iwao Yamazaki , Hitachi, Ltd.
pp. 242

Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis (Abstract)

Ismed Hartanto , Agilent Technologies
Tracy Larrabee , University of California at Santa Cruz
David B. Lavo , Agilent Technologies
pp. 250

An Effective Diagnosis Method to Support Yield Improvement (Abstract)

Rene Segers , Philips Semiconductors
Maurice Lousberg , Philips Research Labs
Stefan Eichenberger , Philips Semiconductors
Camelia Hora , Eindhoven University of Technology
pp. 260
SESSION 10: CONNECTING DISCONNECTS
SESSION 11: TEST DATA COMPRESSION

Embedded Deterministic Test for Low-Cost Manufacturing Test (Abstract)

Rob Thompson , Mentor Graphics Corporation
Grzegorz Mrugalski , Poznan University of Technology
Nilanjan Mukherjee , Mentor Graphics Corporation
Geir Eide , Mentor Graphics Corporation
Mark Kassab , Mentor Graphics Corporation
Nagesh Tamarapalli , Mentor Graphics Corporation
Jun Qian , Cisco Systems
Jerzy Tyzer , Poznan University of Technology
Kun-Han Tsai , Mentor Graphics Corporation
Andre Hertwig , Mentor Graphics Corporation
Januz Rajki , Mentor Graphics Corporation
pp. 301

Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression (Abstract)

Nur A. Touba , University of Texas at Austin
C.V. Krishna , University of Texas at Austin
pp. 321

Multiscan-Based Test Compression and Hardware Decompression Using LZ77 (Abstract)

Francis G. Wolff , Case Western Reserve University
Chris Papachristou , Case Western Reserve University
pp. 331
SESSION 12: LECTURE SERIES — EMBEDDED IP FOR SOC INFRASTRUCTURE
SESSION 13: CHIP-LEVEL CROSSTALK IDENTIFICATION AND TESTING

XIDEN: Crosstalk Target Identification Framework (Abstract)

Sandeep K. Gupta , University of Southern California
Melvin A Breuer , University of Southern California
Suriyaprakash Natarajan , University of Southern California
Shahin Nazarian , University of Southern California
Hang Huang , University of Southern California
pp. 365
SESSION 14: ADVANCES IN FAULT SIMULATION AND TEST GENERATION

On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults (Abstract)

Juhong Zhu , ASP Motorola
Magdy S. Abadir , ASP Motorola
Li-C. Wang , University of California at Santa Barbara
pp. 398

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme (Abstract)

Rohit Kapur , Synopsys Inc.
M. Ray Mercer , Texas A&M University
Jennifer Dworak , Texas A&M University
Li-C. Wang , University of California at Santa Barbara
Jing-Jia Liou , University of California at Santa Barbara
Thomas W. Williams , Synopsys Inc.
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 407
SESSION 15: ADVENTURES IN INTERFACING

Realistic Spring Probe Testing Methods and Results (Abstract)

D. Gessel , Teradyne Integra Test Division
A. Sprunt , Massachusetts Institute of Technology
S. Ziegenhagen , Teradyne Connection Systems
A. Slcoum , Massachusetts Institute of Technology
pp. 417

Low-Contact-Force Probing on Copper Electrodes (Abstract)

Katsuya Okumura , University of Tokyo
Toshihiro Itoh , University of Tokyo
Tadatomo Suga , University of Tokyo
Kenichi Kataoka , University of Tokyo
pp. 424
SESSION 16: DFT TESTERS

Multi-Purpose Digital Test Core Utilizing Programmable Logic (Abstract)

D.C. Keezer , Georgia Institute of Technology
J.S. Davis , Georgia Institute of Technology
pp. 438

Realizing the Benefits of Structural Test for Intel Microprocessors (Abstract)

Navid Shahriari , Intel Corporation
John Johnson , Intel Corporation
Mike Tripp , Intel Corporation
Mike Mayberry , Intel Corporation
pp. 456
SESSION 17: PRODUCTION TEST AUTOMATION

Isolating and Removing Sources of Variation in Test Data (Abstract)

Robert Daasch , Portland State University
James McNames , Portland State University
David Abercrombie , LSI Logic
David Turner , Portland State University
Robert Madge , LSI Logic
pp. 464

System Manufacturing Test Cost Model (Abstract)

David Williams , Dell Computer Corporation and University of Texas at Austin
Anthony P. Ambler , University of Texas at Austin
pp. 482
SESSION 18: SOFT AND HARD FAILURE ANALYSIS AND ON-LINE TESTING

On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips (Abstract)

Sujit Dey , University of California at San Diego
Li Chen , University of California at San Diego
Yi Zhao , University of California at San Diego
pp. 491

Static Analysis of SEU Effects on Software Applications (Abstract)

P. Prinetto , Politecnico di Torino
S. Di Carlo , Politecnico di Torino
A. Benso , Politecnico di Torino
G. Di Natale , Politecnico di Torino
pp. 500

Experimental Evaluation of Scan Tests for Bridges (Abstract)

Eric W Savage , Intel Corporation
Sreejit Chakravarty , Intel Corporation
Ankur Jain , Intel Corporation
Nandakumar Radhakrishnan , Intel Corporation
Sujit T Zachariah , Intel Corporation
pp. 509
SESSION 19: SOC BENCHMARKS

A Set of Benchmarks fo Modular Testing of SOCs (Abstract)

Vikram Iyengar , IBM Microelectronics
Krishnendu Chakrabarty , Duke University
Erik Jan Marinissen , Philips Research Laboratories
pp. 519

Effective and Efficient Test Architecture Design for SOCs (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Erik Jan Marinissen , Philips Research Laboratories
pp. 529

On the Use of k-tuples for SoC Test Schedule Representation (Abstract)

Vikram Iyengar , IBM Microelectronics
Sandeep Koranne , Tanner Research, Inc.
pp. 539
SESSION 20: APPLICATION SERIES — HIGH-SPEED TEST INTERFACES

Physical Principles of Interface Design (Abstract)

Todd Sargent , For Intest Corporation
pp. 549
SESSION 21: TEST AND DEBUG OF MICROPROCESSORS

Test Methodology for Motorola?s High Performance e500 Core Based on PowerPC Instruction Set Architecture (Abstract)

R. Raina , Motorola Inc.
N. Tendolkar , Motorola Inc.
E. Fiene , Motorola Inc.
A. Metayer , Motorola Inc.
E. Wolf , Motorola Inc.
M. Alexander , Motorola Inc.
B. Svrcek , Motorola Inc.
B. Bailey , Motorola Inc.
R. Woltenberg , Motorola Inc.
pp. 574

FRITS — A Microprocessor Functional BIST Method (Abstract)

Kaila Maneparambil , Intel? Corporation
Praveen Parvathala , Intel? Corporation
William Lindsay , Intel? Corporation
pp. 590
SESSION 22: FPGA TESTING

FPGA Test and Coverage (Abstract)

Andrew Lai , Xilinx
pp. 599

Fault Grading FPGA Interconnect Test Configurations (Abstract)

Shahin Toutounchi , Xilinx Inc.
Subhasish Mitra , Intel Corporation
Edward J. McCluskey , Stanford University
Mehdi Baradaran Tahoori , Stanford University
pp. 608

BIST-Based Diagnosis of FPGA Interconnect (Abstract)

Matthew Lashinsky , University of North Carolina at Charlotte
Jeremy Nall , University of North Carolina at Charlotte
Miron Abramovici , Agere Systems
Charles Stroud , University of North Carolina at Charlotte
pp. 618
SESSION 23: LECTURE SERIES — SILICON DEBUG

Facilitating Rapid First Silicon Debug (Abstract)

Neil Simpson , Texas Instruments
Hari Balachandran , Texas Instruments
Kenneth M. Butler , Texas Instruments
pp. 628

Core-Based Scan Architecture for Silicon Debug (Abstract)

Bart Vermeulen , Philips Research Laboratories
Tom Waayers , Philips Research Laboratories
Sandeep Kumar Goel , Philips Research Laboratories
pp. 638

Re-Using DFT Logic for Functional and Silicon Debugging Test (Abstract)

Xinli Gu , Cisco Systems, Inc.
Weili Wang , Cisco Systems, Inc.
Kevin Li , Cisco Systems, Inc.
Heon Kim , Cisco Systems, Inc.
Sung S. Chung , Cisco Systems, Inc.
pp. 648

Silicon Symptoms to Solutions: Applying Design for Debug Techniques (Abstract)

Rekha Bangalore , Motorola, Inc.
Dawit Belete , Motorola, Inc.
Denise Younger , Motorola, Inc.
Jason Goertz , Motorola, Inc.
Carol Pyron , Motorola, Inc.
Ashutosh Razdan , Motorola, Inc.
pp. 664
SESSION 24: DATA ANALYSIS AND YIELD MODEL VALIDATION

Screening MinVDD Outliers Using Feed-Forward Voltage Testing (Abstract)

D. Turner , Portland State University
C. Schuermyer , Portland State University
R. Madge , LSI Logic Corporation
C. Taylor , Portland State University
V. Rajagopalan , LSI Logic Corporation
C. Macchietto , LSI Logic Corporation
B.H. Goh , LSI Logic Corporation
R. Daasch , Portland State University
pp. 673

Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation (Abstract)

Bob Kopitzke , Agilent Technologies Company
Tuan Pham , Agilent Technologies Company
Pete O?Neill , Agilent Technologies Company
Minh Quach , Agilent Technologies Company
Tim Figal , Agilent Technologies Company
pp. 683
SESSION 25: JITTER TESTING IN MULTI-GIGAHERTZ DIGITAL SYSTEMS

Jitter Testing for Multi-Gigabit Backplane SerDes — Techniques to Decompose and Combine Various Types of Jitter (Abstract)

G.J. Zhang , Agere Systems, Inc.
Y. Cai , Agere Systems, Inc.
S.A. Werner , Agere Systems, Inc.
R.D. Brink , Agere Systems, Inc.
M.J. Olsen , Agere Systems, Inc.
pp. 700

On the Accuracy of Jitter Separation from Bit Error Rate Function (Abstract)

Jan B. Wilstrup , Wavecrest Corporation
Mike P. Li , Wavecrest Corporation
pp. 710

A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter (Abstract)

Louis Malarsie , Agere Systems
Hirobumi Musha , Advantest Corporation
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd.
Masahiro Ishida , Advantest Laboratories, Ltd.
Mani Soma , University of Washington
pp. 717
SESSION 26: EFFICIENT APPROACHES TO SOC TESTING

A Scalable,Low Cost Design-for-Test Architecture for UltraSPARC™ Chip Multi-Processors (Abstract)

Ishwar Parulkar , Sun Microsystems, Inc.
Thomas Ziaja , Sun Microsystems, Inc.
Rajesh Pendurkar , Sun Microsystems, Inc.
Anand D'Souza , Sun Microsystems, Inc.
Amitava Majumdar , Sun Microsystems, Inc.
pp. 726

Optimal BIST Using an Embedded Microprocessor (Abstract)

Sungbae Hwang , University of Texas at Austin
Jacob A. Abraham , University of Texas at Austin
pp. 736
SESSION 27: 1149.1 VERIFICATION AND VALIDATION

Improved Digital I/O Ports Enhance Testability of Interconnections (Abstract)

Adam Kristof , Silesian University of Technology
pp. 763

Testing Finite State Machines Based on a Structural Coverage Metric (Abstract)

Sezer G?ren , University of California at Santa Cruz
F. Joel Ferguson , University of California at Santa Cruz
pp. 773
SESSION 28: SCAN STITCHING

An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning (Abstract)

David Berthelot , Magma Design Automation, Inc.
Hamid Savoj , Magma Design Automation, Inc.
Samit Chaudhuri , Magma Design Automation, Inc.
pp. 781

Integrating DFT in the Physical Synthesis Flow (Abstract)

F. Neuveux , Synopsys, Inc.
R. Chandramouli , Synopsys, Inc.
R. Kapur , Synopsys, Inc.
L. Guiller , Synopsys, Inc.
S. Duggirala , Synopsys, Inc.
pp. 788

Power Driven Chaining of Flip-Flops in Scan Architectures (Abstract)

Y. Bonhomme , Universit? Montpellier II /CNRS
S. Pravossoudovitch , Universit? Montpellier II /CNRS
P. Girard , Universit? Montpellier II /CNRS
C. Landrault , Universit? Montpellier II /CNRS
pp. 796

Automatic Scan Insertion and Test Generation for Asynchronous Circuits (Abstract)

Hans Kerkhoff , University of Twente
Marc Verra , Philips Research Laboratories
Kees van Berkel , Philips Research Laboratories and Eindhoven University of Technology
Ad Peeters , Philips Research Laboratories
Frank te Beest , University of Twente
pp. 804
SESSION 29: DFT FOR MANUFACTURING PROBLEMS

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST (Abstract)

M.B. Santos , IST/Inesc-id
S. Manich , Università Politecnica de Catalunya
I.C. Teixeira , IST/Inesc-id
R. Rodriquez , Università Politecnica de Catalunya
J.P. Teixeira , IST/Inesc-id
J. Figueras , Università Politecnica de Catalunya
pp. 814

An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes (Abstract)

Sandeep K. Gupta , University of Southern California
Zhigang Jiang , University of Southern California
pp. 824

Scan Power Reduction Through Test Data Transition Frequency Analysis (Abstract)

Ismet Bayraktaroglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
Ozgur Sinanoglu , University of California at San Diego
pp. 844
SESSION 30: MIXED-SIGNAL TEST TECHNIQUES

A New Test Generation Approach for Embedded Analogue Cores in SoC (Abstract)

L. Fang , University of Twente
M. Stancic , University of Twente
R. M. W. Tijink , University of Twente
M. H. H. Weusthof , University of Twente
H. G. Kerkhoff , University of Twente
pp. 861

Test Setup Simulation — A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements (Abstract)

Hermann Tauber , Infineon Technologies Microelectronic Design Centers Austria GmbH
Marco Rona , Infineon Technologies Microelectronic Design Centers Austria GmbH
Gunter Krampl , Infineon Technologies Microelectronic Design Centers Austria GmbH
pp. 870
SESSION 31: GO-FAST ATE!

CMOS Circuit Technology for Precise GHz Timing Generator (Abstract)

Masakatsu Suda , ADVANTEST Corporation
Toshiyuki Okayasu , ADVANTEST Corporation
Kazuhiro Yamamoto , ADVANTEST Corporation
pp. 894
SESSION 32: SYSTEM TEST DESIGN, BIST AND SYSTEM VERIFICATION

Efficient Design of System Test: A Layered Architecture (Abstract)

Alfredo Benso , Politecnico di Torino
Andrea Taddei , Magneti Marelli Electronic Systems
Sergio Mo , Magneti Marelli Electronic Systems
Andrea Baldini , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
pp. 930

Itelligent Agents and BIST/BISR — Working Together in Distributed Systems (Abstract)

Alfredo Benso , Politecnico di Torino
Enyedi Szil?rd , Technical University of Cluj-Napoca
Liviu Miclea , Technical University of Cluj-Napoca
pp. 940
SESSION 33: ADVANCES IN I<sub>DDX</sub>

Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs (Abstract)

B. Alorda , University Illes Balears
M. Rosales , University Illes Balears
C. Hawkins , University of New Mexico
J. Segura , University Illes Balears
J. Soden , Sandia National Laboratories
pp. 947

Improved I<sub>DDQ</sub> Testing with Empirical Linear Prediction (Abstract)

Hans Engler , Georgetown University
David I. Bergman , National Institute of Standards and Technology
pp. 954

Comparison of I<sub>DDQ</sub> Testing and Very-Low Voltage Testing (Abstract)

Bram Kruseman , Philips Research Laboratories
Josep Rius , DEE of Universitat Politecnica de Catalunya
Stefan van den Oetelaar , Philips Research Laboratories
pp. 964
SESSION 34: DELAY-TEST

Finding a Small Set of Longest Testable Paths that Cover Every Gate (Abstract)

Janak H. Patel , University of Illinois at Urbana Champaign
Manish Sharma , University of Illinois at Urbana Champaign
pp. 974

Techniques to Reduce Data Volume and Application Time for Transition Test (PDF)

Paul J. Thadikaran , Virginia Tech and Intel Corporation
Sreejit Chakravarty , Virginia Tech and Intel Corporation
Michael Hsiao , Virginia Tech
Xiao Liu , Virginia Tech
pp. 983
SESSION 35: EMBEDDED TEST FOR ANALOG AND DIGITAL

Application of High-Quality Built-In Test to Industrial Designs (Abstract)

Takaharu Nagumo , Hitachi, Ltd.
Koichiro Natsume , Hitachi, Ltd.
Kazumi Hatayama , Hitachi, Ltd.
Michinobu Nakao , Hitachi, Ltd.
Yasuo Sato , Hitachi, Ltd.
Yoshikazu Kiyoshige , Hitachi, Ltd.
pp. 1003

Pseudo Random Patterns Using Markov Sources for Scan BIST (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
Nadir Z. Basturkmen , University of Iowa
pp. 1013
SESSION 36: MAXIMIZING TEST EFFECTIVENESS AND MINIMIZING COST

High Accuracy Stimulus Generation for A/D Converter BIST (Abstract)

Davide Appello , STMicroelectronics
Stephen Sunter , LogicVision (Canada), Inc.
Aubin Roy , LogicVision (Canada), Inc.
Alessandra Fudoli , STMicroelectronics
pp. 1031

Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits (Abstract)

Carol Pyron , Motorola Inc.
Lee Song , Teradyne Inc.
John Gatej , Teradyne Inc.
Tom Munns , Motorola Inc.
Rajesh Raina , Motorola Inc.
pp. 1040
SESSION 37: BOARD TEST AND BIST FOR MEMS

IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks (Abstract)

Ken Parker , Agilent Technologies
Bill Eklow , Cisco Systems Inc.
pp. 1056

Test Coverage: What Does It Mean When a Board Test Passes? (Abstract)

Kathy Hird , Agilent Technologies
Bill Follis , Agilent Technologies
Kenneth P. Parker , Agilent Technologies
pp. 1066

Built-In Self Test of CMOS-MEMS Accelerometers (Abstract)

N. Deb , Carnegie Mellon University
R.D. (Shawn) Blanton , Carnegie Mellon University
pp. 1075
SESSION 38: DEBUG AND DIAGNOSIS

Incremental Diagnosis of Multiple Open-Interconnects (Abstract)

Hiroshi Takahashi , Ehime University
J. Brandon Liu , University of Toronto
Andreas Veneris , University of Toronto
pp. 1085

Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
pp. 1103
SESSION 39: DELAY-TEST: PRACTICAL EXPERIENCE AND SOLUTIONS

Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor (Abstract)

Rajesh Raina , Motorola Inc.
William Schwarz , Motorola Inc.
Jeff Morehead , Motorola Inc.
Christopher Hawkins , Motorola Inc.
Ashutosh Razdan , Motorola Inc.
Dawit Belete , Motorola Inc.
pp. 1111

Scan-Based Transition Fault Testing — Implementation and Low Cost Test Challenges (Abstract)

R Raghuraman , Texas Instruments Inc.
John Berech , Texas Instruments Inc.
David J. Campbell , Texas Instruments Inc.
Sudheendra Phani Kumar , Texas Instruments Inc.
Jayashree Saxena , Texas Instruments Inc.
Kenneth M. Butler , Texas Instruments Inc.
John Gatt , Texas Instruments Inc.
Supatra Basu , Texas Instruments Inc.
pp. 1120
SESSION 40: RF TESTING

WCDMA Testing with a Baseband/IF Range AWG (Abstract)

Motoo Ueda , Advantest America, Inc.
Karl Watanabe , Advantest America, Inc.
Toshifumi Watanabe , Advantest America, Inc.
Yasuo Furukawa , Advantest Gunma R&D Center
Michael Purtell , Advantest America, Inc.
Koji Asami , Advantest Gunma R&D Center
pp. 1140

Architecting Millisecond Test Solutions for Wireless Phone RFIC?s (Abstract)

Steve Moss , IBM RF & Analog Test Development
Randy Wolf , IBM RF & Analog Test Development
John Ferrario , IBM RF & Analog Test Development
pp. 1151
SESSION 41: TEST RESOURCE PARTITIONING

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints (Abstract)

Vikram Iyengar , IBM Microelectronics
Erik Jan Marinissen , Philips Research Laboratories
Sandeep Kumar Goel , Philips Research Laboratories
Krishnendu Chakrabarty , Duke University
pp. 1159

Adapting an SoC to ATE Concurrent Test Capabilities (Abstract)

Rainer Dorsch , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
Martin Fischer , Agilent Technologies
Ram?n Huerta Rivera , University of Stuttgart
pp. 1169

Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores (Abstract)

Mohsen Nahvi , University of British Columbia
Andr? Ivanov , University of British Columbia
Resve Saleh , University of British Columbia
pp. 1176
PANEL 1: CAN SYSTEM TEST AND IC TEST LEARN FROM EACH OTHER?

Test Coverage Models for System Test? (PDF)

David Williams , Dell Computer Corporation and University of Texas at Austin
pp. 1185

Can IC Test Learn from How a Tester is Tested (PDF)

Rochit Rajsuman , Advantest America R & D Center Inc.
pp. 1186

What Can IC Test Teach System Test? (PDF)

Scott Davidson , Sun Microsystems Inc.
pp. 1187

Is It Rocket Science? (PDF)

Anthony P. Ambler , University of Texas at Austin
pp. 1188
PANEL 2: TAPS ALL OVER MY CHIPS

Inevitable Use of TAP Domains in SOCs (PDF)

Lee Whetsel , Texas Instruments
pp. 1191

TAPs All Over My Chips (PDF)

Steven F. Oakland , IBM Microelectronic Division
pp. 1192
PANEL 3: CAN SCAN ACHIEVE THE QUALITY LEVEL WE ARE LOOKING FOR?

Trouble With Scan (PDF)

David M. Wu , Intel
pp. 1199
PANEL 4: MIXED-SIGNAL BIST: FACT OR FICTION?

A/MS BISTs: The FACTS, Just the Facts (PDF)

Arnold Frisch , Integrated Measurement Systems™, Inc. A Credence Company
pp. 1201

Mixed-Signal BIST: Fact or Fiction (PDF)

Karim Arabi , PMC Sierra, Inc.
pp. 1202
PANEL 5: MISSION POSSIBLE?: AN OPEN ATE TESTER ARCHITECTURE

Mission Impossible? Open Architecture ATE (PDF)

Dennis R. Conti , IBM Microelectronic Division
pp. 1207

Mission Possible? Open Architecture ATE (PDF)

Paul F. Scrivens , Third Millennium Test Solutions
pp. 1208

The Consequences of an Open ATE Architecture (PDF)

Sergio M Perez , Advantest America, Inc.
pp. 1210
PANEL 6: THE IMPACTS OF OUTSOURCING ON TEST

The Yield of Test Outsourcing (PDF)

Davide Appello , STMicroelectronics
pp. 1215

The Impact of Outsourcing on Test (PDF)

Fidel Muradali , Agilent Technologies
pp. 1216

Outsourcing Test without Standards? (PDF)

Peter Muhmenthaler , Infineon Technologies AG
pp. 1217
PANEL 7: TEST AND REPAIR OF COMMODITY AND EMBEDDED FLASH MEMORIES
PANEL 8: TESTING HIGHLY INTEGRATED CIRCUITS AND SYSTEMS USING A LOW-COST TESTER:HOW TO OVERCOME THE CHALLENGE?
PANEL 9: MULTI-GHZ ERA: TEST CHALLENGES AND SOLUTIONS

GHz Testing and Its Fuzzy Targets (PDF)

J. Segura , Balearic Islands University
C. Hawkins , University of New Mexico
pp. 1228

Challenges and Solutions for Multi-Gigahertz Testing (PDF)

D. C. Keezer , Georgia Institute of Technology
pp. 1230
PANEL 10: BOARD TEST AND ITC: WHAT DOES THE FUTURE HOLD?

Is Board Test Worth Talking About? (PDF)

Bill Eklow , Cisco Systems, Inc.
pp. 1235

Board Test: Wanted Dead or Alive (PDF)

Gordon D Robinson , Third Millennium Test Solutions
pp. 1236

Is ITC Bored with Board Test? (PDF)

Kenneth M. Butler , Texas Instruments Inc.
pp. 1237

Board Test Is NOT Mature (PDF)

Kenneth P. Parker , Agilent Technologies
pp. 1238
2001 ITC BEST PAPER:

Neighbor Selection for Variance Reduction in I<sub>DDQ</sub> and Other Parametric Data (Abstract)

James McNames , Portland State University
W. Robert Daasch , Portland State University
Robert Madge , LSI Logic Corporation
Kevin Cota , Portland State University
pp. 1240
90 ms
(Ver )