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Proceedings. International Test Conference (2002)
Baltimore, MD, USA
Oct. 7, 2002 to Oct. 10, 2002
ISBN: 0-7803-7543-2
pp: 1103
Sandeep Kumar Goel , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
ABSTRACT
To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and the memory elements is observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data. The phenomenon of capturing old data is called as data invalidation. This paper describes the data invalidation problem in depth and presents a data invalidation detector circuit. An automated hierarchical data invalidation analysis tool named DIAna is also presented. By means of experimental results for two industrial SOCs, we show the amount of data invalidation that can occur during silicon debug.
INDEX TERMS
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CITATION

S. K. Goel and B. Vermeulen, "Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips," Proceedings. International Test Conference(ITC), Baltimore, MD, USA, 2002, pp. 1103.
doi:10.1109/TEST.2002.1041867
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