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Proceedings. International Test Conference (2002)
Baltimore, MD, USA
Oct. 7, 2002 to Oct. 10, 2002
ISBN: 0-7803-7543-2
pp: 974
Manish Sharma , University of Illinois at Urbana Champaign
Janak H. Patel , University of Illinois at Urbana Champaign
Testing the longest path passing through each gate is important to detect small localized delay defects at a gate, e.g. resistive opens or resistive shorts. In this paper we present ATPG techniques to automatically determine the longest testable path passing through a gate or wire in the circuit without first listing all long paths passing through it. This technique is based on a graph traversal algorithm that can traverse all paths of a given length in a weighted directed acyclic graph. Experimental results for ISCAS benchmarks are also presented.

J. H. Patel and M. Sharma, "Finding a Small Set of Longest Testable Paths that Cover Every Gate," Proceedings. International Test Conference(ITC), Baltimore, MD, USA, 2002, pp. 974.
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