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2013 IEEE International Test Conference (ITC) (2002)
Baltimore, MD, USA
Oct. 7, 2002 to Oct. 10, 2002
ISBN: 0-7803-7543-2
pp: 974
Janak H. Patel , University of Illinois at Urbana Champaign
Manish Sharma , University of Illinois at Urbana Champaign
ABSTRACT
Testing the longest path passing through each gate is important to detect small localized delay defects at a gate, e.g. resistive opens or resistive shorts. In this paper we present ATPG techniques to automatically determine the longest testable path passing through a gate or wire in the circuit without first listing all long paths passing through it. This technique is based on a graph traversal algorithm that can traverse all paths of a given length in a weighted directed acyclic graph. Experimental results for ISCAS benchmarks are also presented.
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CITATION
Janak H. Patel, Manish Sharma, "Finding a Small Set of Longest Testable Paths that Cover Every Gate", 2013 IEEE International Test Conference (ITC), vol. 00, no. , pp. 974, 2002, doi:10.1109/TEST.2002.1041853
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