2013 IEEE International Test Conference (ITC) (2002)
Baltimore, MD, USA
Oct. 7, 2002 to Oct. 10, 2002
Rohit Kapur , Synopsys Inc.
M. Ray Mercer , Texas A&M University
Jennifer Dworak , Texas A&M University
Li-C. Wang , University of California at Santa Barbara
Jing-Jia Liou , University of California at Santa Barbara
Thomas W. Williams , Synopsys Inc.
Kwang-Ting Cheng , University of California at Santa Barbara
In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern set and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.
Rohit Kapur, M. Ray Mercer, Jennifer Dworak, Li-C. Wang, Jing-Jia Liou, Thomas W. Williams, Kwang-Ting Cheng, "Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme", 2013 IEEE International Test Conference (ITC), vol. 00, no. , pp. 407, 2002, doi:10.1109/TEST.2002.1041786