The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2001)
Baltimore, Maryland
Oct. 30, 2001 to Nov. 1, 2001
ISBN: 0-7803-7171-2
TABLE OF CONTENTS
INTRODUCTORY SECTION

Author Index (PDF)

pp. 1200
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?

Bridging the Gap (PDF)

Lori Watrous-deVersterre , Mentor Graphics Corporation
pp. 27
SPECIAL PANEL: STRUCTURED TEST: THEN AND NOW

STRUCTURED TEST: THEN AND NOW (PDF)

Robert C. Aitken , Agilent Technologies
pp. 28
SESSION 1: PLENARY

null (PDF)

pp. null

Keynote Address: Test Trade-offs: The View from Wall Street (PDF)

Sue Billat , Robertson Stephens Investment Bankers
pp. 12
SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST

null (PDF)

pp. null

AC-JTAG: Empowering JTAG beyond Testing DC Nets (Abstract)

Sang H. Baeg , Cisco Systems, Inc.
Sung S. Chung , Cisco Systems, Inc.
pp. 30

A General Purpose 1149.4 IC with HF Analog Test Capabilities (Abstract)

Ken Filliter , National Semiconductor Corp.
Pat McHugh , Lockheed Martin - EPI
Joe Woo , Lockheed Martin - EPI
Stephen Sunter , LogicVision, Inc.
pp. 38

Frequency Detection-Based Boundary-Scan Testing of AC Coupled Nets (Abstract)

Kenneth P. Parker , Agilent Technologies
Young Kim , Agilent Technologies
Benny Lai , Agilent Technologies
Jeff Rearick , Agilent Technologies
pp. 46
SESSION 3: BIST MEDLEY

null (PDF)

pp. null

At-Speed Logic BIST Using a Frozen Clock Testing Strategy (Abstract)

Jongshin Shin , University of Illinois at Urbana-Champaign
Miron Abramovici , Agere Systems
Elizabeth M. Rudnick , University of Illinois at Urbana-Champaign
Xiaoming Yu , University of Illinois at Urbana-Champaign
pp. 64
SESSION 4: HOW CAN WE INPROVE I<sub>DDQ</sub> TESTING FOR DSM/VDSM?

null (PDF)

pp. null

Improved Wafer-level Spatial Analysis for IDDQ Limit Setting (Abstract)

D.M.H. Walker , Texas A&M University
Sagar Sabade , Texas A&M University
pp. 82

NEIGHBOR SELECTION FOR VARIANCE REDUCTION IN I<sub>DDQ</sub> and OTHER PARAMETRIC DATA (Abstract)

Kevin Cota , Portland State University
James McNames , Portland State University
W. Robert Daasch , Portland State University
Robert Madge , LSI Logic Corporation
pp. 92

The Future of Delta I<sub>DDQ</sub> Testing (Abstract)

Bram Kruseman , Philips Research Laboratories
Rutger van Veen , Philips Research Laboratories
Kees van Kaam , Philips Research Laboratories
pp. 101
SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING

null (PDF)

pp. null

Test and Debug Strategy of the PNX8525 Nexperia™ Digital Video Platform System Chip (Abstract)

Frank Bouwman , Philips Semiconductors North America
Bart Vermeulen , Philips Research Laboratories
Steven Oostdijk , Philips Semiconductors North America
pp. 121

CTL the Language for Describing Core-Based Test (Abstract)

Tony Taylor , Synopsys Inc.
Paul Reuter , Mentor Graphics
Douglas Kay , Cisco
Rohit Kapur , Synopsys Inc.
pp. 131
SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE

null (PDF)

pp. null

Split Timing Mode (STM) - Answer To Dual Frequency Domain Testing (Abstract)

A.T. Sivaram , Schlumberger Semiconductor Solutions
pp. 140

Automated Translation of Legacy Code for ATE (Abstract)

Emir Pasalic , Oregon Graduate Institute
Andrew Gill , Galois Connections Inc.
Jim Teisher , Galois Connections Inc.
Andrew Moran , Galois Connections Inc.
John Veneruso , Credence Systems Corporation
pp. 148

REMOTE ACCESS TO ENGINEERING TEST — A CASE STUDY IN PROVIDING ENGINEERING/DIAGNOSTIC IC TEST SERVICES TO CANADIAN UNIVERSITIES (Abstract)

C. J. Verver , Communications Research Centre
M. E. Jarosz , Canadian Microelectronics Corporation
R. L. Stevenson , Canadian Microelectronics Corporation
pp. 157
SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS

null (PDF)

pp. null

Test and Repair of Large Embedded DRAMs: Part 1 (Abstract)

Erik Nelson , IBM Microelectronics
Rochit Rajsuman , Advantest America
Roderick McConnell , Infineon Technologies,
Jeffrey Dreibelbis , IBM Microelectronics
pp. 163

Test and Repair of Large Embedded DRAMs: part 2 (Abstract)

Jeffrey Dreibelbis , IBM Microelectronics
Erik Nelson , IBM Microelectronics
Roderick McConnell , Infineon Technologies
pp. 173

Test cost reduction by at-speed BISR for embedded DRAMs (Abstract)

Kazutami Arimito , Mitsubishi Electric Corp.
Michael Mullins , Mitsubishi Electronics America, Inc.
Tatsunori Komoike , Mitsubishi Electric Corp.
Katsumi Dosaka , Mitsubishi Electric Corp.
Anthony Sauvageau , Mitsubishi Electronics America, Inc.
Tetsushi Tanizaki , Mitsubishi Electric Corp.
Tetsuo Tada , Mitsubishi Electric Corp.
Yoshinori Fujiwara , Mitsubishi Electric Corp.
Katsuya Furue , Mitsubishi Electric Corp.
Yoshihiro Nagura , Mitsubishi Electric Corp.
Ryuji Ohmura , Mitsubishi Electric Corp.
Takenori Okitaka , Mitsubishi Electric Corp.
Yukiyoshi Koda , Mitsubishi Electric Corp.
pp. 182
SESSION 8: DFT INNOVATIONS

null (PDF)

pp. null

DPDAT: DATA PATH DIRECT ACCESS TESTING (Abstract)

Kee Sup Kim , Intel Corporation
Adrian Carbine , Intel Corporation
Craig Carstens , Intel Corporation
Derek Feltham , Intel Corporation
Rathish Jayabharathi , Intel Corporation
Praveen Vishakantaiah , Intel Corporation
pp. 188

Contactless Digital Testing of IC Pin Leakage Currents (Abstract)

Givargis Danialy , LogicVision, Inc.
Charles McDonald , LogicVision, Inc.
Stephen Sunter , LogicVision, Inc.
pp. 204
SESSION 9: ON-LINE TEST

null (PDF)

pp. null

A Highly-Efficient Transparent Online Memory Test (Abstract)

Karl Thaller , Vienna University ofTechnology
pp. 230

GRAAL: a Tool for Highly Dependable SRAMs Generation (Abstract)

Silvia CHIUSANO , Politecnico di Torino
Giorgio DI NATALE , Politecnico di Torino
Franco BIGONGIARI , Aurelia Microelectronica
Paolo PRINETTO , Politecnico di Torino
pp. 250
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS

null (PDF)

pp. null

Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Wojciech Maly , Carnegie Mellon University
Saghir Shaikh , Intel Corporation
Ken Walker , Intel Corporation
John T Chen , Carnegie Mellon University
Jitendra Khare , Intel Corporation
pp. 258

Making Cause-Effect Cost Effective: Low-Resolution Fault Dictionaries (Abstract)

Tracy Larrabee , University of California at Santa Cruz
David B. Lavo , Agilent Technologies
pp. 278

Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm (Abstract)

Leendert Huisman , IBM Microelectronics Division
Thomas Bartenstein , IBM Microelectronics Division
David Sliwinski , IBM Microelectronics Division
Douglas Heaberlin , IBM Microelectronics Division
pp. 287
SESSION 11: TESTING ABOVE A GIGAHERTZ

null (PDF)

pp. null

Testing Interconnects for Noise and Skew in Gigahertz SoCs (Abstract)

Mehrdad Nourani , University of Texas at Dallas
Amir Attarha , University of Texas at Dallas
pp. 305

A BUILT-IN TIMING PARAMETRIC MEASUREMENT UNIT (Abstract)

Jing-Reng Huang , National Tsing-Hua University
Tsin-Yuan Chang , National Tsing-Hua University
Shao-Shen Yang , National Tsing-Hua University
Ming-Jun Hsiao , National Tsing-Hua University
pp. 315

Testing Clock Distribution Circuits Using an Analytic Signal Method (Abstract)

Rajesh Raina , Motorola Inc.
Masahiro Ishida , Advantest Laboratories, Ltd.
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd.
Jim Nissen , Motorola Inc.
Mani Soma , University of Washington
David Halter , Motorola Inc.
pp. 323
SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES

null (PDF)

pp. null

Rapid Prototyping of Time-based PDIT for Substrate Networks (Abstract)

Aranggan Venkataratnam , Rochester Institute of Technology
Kimberly E. Newman , Rochester Institute of Technology
pp. 332

Estimating Burn-In Fall-Out for Redundant Memory (Abstract)

Adit D. Singh , Auburn University
Victor P. Nelson , Auburn University
Thomas S. Barnett , Auburn University
pp. 340
SESSION 13: HIGH-QUALITY TEST

null (PDF)

pp. null

Multiple-Output Propagation Transition Fault Test (Abstract)

Chao-Wen Tseng , Stanford University
Edward J. McCluskey , Stanford University
pp. 358
SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES

null (PDF)

pp. null

Practical Application of Energy Consumption Ratio Test (Abstract)

Eric Peterson , Guidant Corporation
Wanli Jiang , Guidant Corporation
pp. 386

Detecting Delay Faults using Power Supply Transient Signal Analysis (Abstract)

Shirong Liao , University of Maryland, Baltimore County
Abhishek Singh , University of Maryland, Baltimore County
Anne Gattiker , IBM Austin Research Lab
Jim Plusquellic , University of Maryland, Baltimore County
Chintan Patel , University of Maryland, Baltimore County
pp. 395

A Practical Built-In Current Sensor for I<sub>DDQ</sub> Testing (Abstract)

Hoki Kim , Texas A&M University
D.M.H. Walker , Texas A&M University
David Colby , Texas Instruments
pp. 405
SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS

null (PDF)

pp. null

TEST PATH SIMULATION AND CHARACTERISATION (Abstract)

Klaus Helmreich , Advantest Test Engineering Solutions GmbH
pp. 415

Testing beyond EPA: TDF Methodology Solutions Matrix (Abstract)

Sunil K. Jain , Intel Corporation
Greg P. Chema , Intel Corporation
pp. 424

Practical,Non-invasive Optical Probing for Flip-Chip Devices (Abstract)

N. Goldblatt , Schlumberger Probe Systems
G. Dajee , Schlumberger Probe Systems
T. Lundquist , Schlumberger Probe Systems
K. Wilsher , Schlumberger Probe Systems
S. Kasapi , Schlumberger Probe Systems
pp. 433
SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES

null (PDF)

pp. null

Debug Methodology for the McKinley Processor (Abstract)

Steve Poehlman , Intel Corporation
Vincent Govan , Hewlett-Packard Company
Don Douglas Josephson , Hewlett-Packard Company
pp. 451

Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability (Abstract)

Knut Schünemann , IBM Deutschland Entwicklung GmbH
Gundolf Kiefer , University of Stuttgart
Thomas Schwarz , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
Michael Kessler , IBM Deutschland Entwicklung GmbH
Jens Leenstra , IBM Deutschland Entwicklung GmbH
pp. 461
SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS

null (PDF)

pp. null

Hierarchical Boundary-Scan A Scan Chip-Set Solution (Abstract)

Stephen Harrison , Motorola
Peter Horwood , Firecron Ltd
Peter Collins , JTAG Technologies
Greg Noeninckx , Motorola
pp. 480
SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES

null (PDF)

pp. null

A Method to Improve SFDR with Random Interleaved Sampling Method (Abstract)

Hideharu Munakata , Agilent Technologies Japan, Ltd
Atsushi Shimizu , Agilent Technologies Japan, Ltd
Mamoru Tamba , Agilent Technologies Japan, Ltd
Takanori Komuro , Agilent Technologies Japan, Ltd
pp. 512
SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING

null (PDF)

pp. null

Space and Time Compaction Schemes for Embedded Cores (Abstract)

Alex Orailoglu , University of California, San Diego
Ozgur Sinanoglu , University of California, San Diego
pp. 521

Tailoring ATPG for Embedded Testing (Abstract)

Hans-Joachim Wunderlich , University of Stuttgart
Rainer Dorsch , University of Stuttgart
pp. 530

A Case Study on t e Implementation of t e Illinois Scan Architecture (Abstract)

Frank F. Hsu , Texas Instruments Inc.
Kenneth M. Butler , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 538
SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS

null (PDF)

pp. null

Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles
Liang-Chi Chen , University of Southern California, Los Angeles
T. M. Mak , Intel Corporation
Melvin A. Breuer , University of Southern California, Los Angeles
pp. 548

Delay Testing Considering Crosstalk-Induced Effects (Abstract)

Angela Krstic , University of California, Santa Barbara
Jing-Jia Liou , University of California, Santa Barbara
Yi-Min Jiang , Synopsys, Inc.
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 558

On Reducing the Target Fault List of Crosstalk-Induced Delay Faults in Synchronous Sequential Circuits (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison
Yuzo Takamatsu , Ehime University
Hiroshi Takahashi , Ehime University
Keith J. Keller , University of Wisconsin-Madison
pp. 568
SESSION 21: MICROPROCESSOR TESTING

null (PDF)

pp. null

Test Methodology for the McKinley Processor (Abstract)

Steve Poehlman , Intel Corporation
Clint Mumford , Hewlett-Packard Company
Vincent Govan , Hewlett-Packard Company
Don Douglas Josephson , Hewlett-Packard Company
pp. 578
SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT

null (PDF)

pp. null

TOWARDS A UNIFIED TEST PROCESS: FROM UML TO END-OF-LINE FUNCTIONAL TEST (Abstract)

Andrea BALDINI , Politecnico di Torino
Paolo PRINETTO , Politecnico di Torino
Alfredo BENSO , Politecnico di Torino
Sergio MO , Magneti Marelli Electronic Systems
Andrea TADDEI , Magneti Marelli Electronic Systems
pp. 600

DYNAMIC TESTS IN COMPLEX SYSTEMS (Abstract)

Robert Tappe , AUDI AG Ingolstadt, Germany
Dietmar Ehrhardt , University of Siegen, Germany
pp. 609

Unsafe Board States During PC-Based Boundary-Scan Testing (Abstract)

Bill Eklow , Cisco Systems Inc.
Toai Vo , Cisco Systems Inc.
Richard Sedmak , Self Test Services, voice net
Dan Singletary , Cisco Systems Inc.
pp. 615
SESSION 23: DELAY TEST

null (PDF)

pp. null

Too Much Delay Fault Coverage Is a Bad Thing (Abstract)

Jeff Rearick , Agilent Technologies
pp. 624

TESTING OF CRITICAL PATHS FOR DELAY FAULTS (Abstract)

Janak H. Patel , University of Illinois at Urbana Champaign
Manish Sharma , University of Illinois at Urbana Champaign
pp. 634

Exact Path Delay Grading with Fundamental BDD Operations (Abstract)

S. Tragoudas , Southern Illinois University
M. Michael , Southern Illinois University
S. Padmanaban , Southern Illinois University
pp. 642
SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION

null (PDF)

pp. null

Scan Array Solution for Testing Power and Testing Time (Abstract)

Lei Xu , Tsinghua University
Yihe Sun , Tsinghua University
Hongyi Chen , Tsinghua University
pp. 652

A Token Scan Architecture for Low Power Testing (Abstract)

Kuen-Jong Lee , National Cheng Kung University
Tsung-Chu Huang , National Cheng Kung University
pp. 660

An Analysis of Powe Reduction Techniques in Scan Testing (Abstract)

Kenneth M. Butler , Texas Instruments Inc.
Lee Whetsel , Texas Instruments Inc.
Jayashree Saxena , Texas Instruments Inc.
pp. 670
SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL

null (PDF)

pp. null

A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPU (Abstract)

A.B. Ma , Intel Corporation
V. Krishnaswamy , Intel Corporation
P. Vishakantaiah , Intel Corporation
pp. 688

FedEx - A Fast Bridging Fault Extractor (Abstract)

D.M.H. Walker , Texas A&M University
Zoran Stanojevic , Texas A&M University
pp. 696
SESSION 26: ATE HW: CONQUERING THOSE STUBBORN TEST PROBLEMS

null (PDF)

pp. null

Power Supply Transient Signal Integration Circuit (Abstract)

Chintan Patel , University of Maryland, Baltimore County
Jim Plusquellic , University of Maryland, Baltimore County
Fidel Muradali , University of Maryland, Baltimore County
pp. 704

Scan Test Sequencing Hardware for Structural Test (Abstract)

Jamie Cullen , Schlumberger Semiconductor Solutions
pp. 713
SESSION 27: ADVANCES IN SCAN TESTING

null (PDF)

pp. null

Tester Retargetable Patterns (Abstract)

Rohit Kapur , Synopsys, Inc.
T. W. Williams , Synopsys, Inc.
pp. 721

On RTL Scan Design (Abstract)

Omer Samman , Mentor Graphics Corporation
Chien-Chung Tsai , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Nilanjan Mukherjee , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa, Iowa City
Yu Huang , University of Iowa, Iowa City
Dan Devries , Mentor Graphics Corporation
pp. 728

Enhanced Reduced Pin-Count Test for Full-Scan Design (Abstract)

Harald Vranken , Philips Research Laboratories
Hervé Fleury , Philips Semiconductors
David Lelouvier , Philips Semiconductors
Tom Waayers , Philips Research Laboratories
pp. 738

OPMISR: The Foundation for Compressed ATPG Vectors (Abstract)

Owen Farnsworth , IBM Microelectronics
Carl Barnhart , IBM Microelectronics
Brion Keller , IBM Microelectronics
Frank Distler , IBM Microelectronics
Vanessa Brunkhorst , IBM Microelectronics
Bernd Koenemann , IBM Microelectronics
pp. 748
SESSION 28: MEMORY TESTING

null (PDF)

pp. null

March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults (Abstract)

Chih-Tsun Huang , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Jin-Fu Li , National Tsing Hua University
pp. 758

BITLINE CONTACTS IN HIGH DENSITY SRAMS: DESIGN FOR TESTABILITY AND STRESSABILITY (Abstract)

Harold Pilo , IBM Microelectronics Division
George E. Rudgers , IBM Microelectronics Division
Erik A. Nelson , IBM Microelectronics Division
Robert E. Busch , IBM Microelectronics Division
R. Dean Adams , IBM Microelectronics Division
pp. 776

Simulation Based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs (Abstract)

Detlev Richter , Infineon Technologies AG
Zaid Al-Ars , Delft University of Technology
Jens Braun , Infineon Technologies AG
Ad J. van de Goor , Delft University of Technology
pp. 783
SESSION 29: INCREASING DESIGN VALIDATION COVERAGE

null (PDF)

pp. null

Cost Evaluation of Coverage Directed Test Generation for the IBM Mainframe (Abstract)

Steven Mittermaier , IBM Corporation
Shmuel Ur , IBM Corporation
Avi Ziv , IBM Corporation
Gilly Nativ , IBM Corporation
pp. 793

A Validation Fault Model for Timing-Induced Functional Errors (Abstract)

Ian G. Harris , University of Massachusetts
Qiushuang Zhang , University of Massachusetts
pp. 813

AMLETO: A Multi-language Environment for Functional Test Generation (Abstract)

Graziano Pravadelli , Universit? di Verona, Italy
Franco Fummi , Universit? di Verona, Italy
Alessandro Fin , Universit? di Verona, Italy
pp. 821
SESSION 30: PLL AND JITTER TESTING

null (PDF)

pp. null

Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL (Abstract)

Seongwon Kim , University of Washington, Seattle
Mani Soma , University of Washington, Seattle
pp. 830
SESSION 31: NEW IDEAS FOR BIST TPG

null (PDF)

pp. null

A New Multiple Weight Set Calculation Algorithm (Abstract)

Jin-kyue Lee , Yonsei Univ.
Hong-Sik Kim , Yonsei Univ.
Sungho Kang , Yonsei Univ.
pp. 878

Test Vector Encodin Usin Partial LFSR Reseedin (Abstract)

C. V. Krishna , University of Texas, Austin
Abhijit Jas , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 885

TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST (Abstract)

Sybille Hellebrand , University of Innsbruck, Austria
Hua-Guo Liang , University of Stuttgart, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Germany
pp. 894
SESSION 32: TEST AUTOMATION, IMPROVING IC TEST EFFICIENCY

null (PDF)

pp. null

Rapid-Response Temperature Control Provides New Defect Screening Opportunities (Abstract)

Burnell G. West , Schlumberger Semiconductor Solutions
Mark Malinoski , Delta Design Columbus
pp. 903

A New Methodology for Improved Tester Utilization (Abstract)

Ajay Khoche , Agilent Technologies Inc.
T. W. Williams , Synopsys Inc.
Mick Tegethoff , Agilent Technologies Inc.
Jochen Rivoir , Agilent Technologies Inc.
Rohit Kapur , Synopsys Inc.
David Armstrong , Agilent Technologies Inc.
pp. 916
SESSION 33: FPGA TESTING

null (PDF)

pp. null

IS-FPGA : A New Symmetric FPGA Architecture with Implicit SCAN (Abstract)

Y. Zorian , Logic Vision Inc.
P. Faure , LIRMM-UM2
J.M. Portal , LIRMM-UM2
M. Renovell , LIRMM-UM2
pp. 924

BIST-Based Delay Path Testing in FPGA Architectures (Abstract)

Russell Tessier , University of Massachusetts at Amherst
Premachandran R. Menon , University of Massachusetts at Amherst
Ian G. Harris , University of Massachusetts at Amherst
pp. 932

On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems (Abstract)

Cecilia Metra , D.E.I.S. University of Bologna
Andrea Pagano , D.E.I.S. University of Bologna
Bruno Riccò , D.E.I.S. University of Bologna
pp. 939
SESSION 34: RF TESTING

null (PDF)

pp. null
SESSION 35: EMBEDDED MEMORIES TEST AND REPAIR

null (PDF)

pp. null

Embedded DRAM Built In Self Test and Methodology for Test Insertion (Abstract)

Michael Nelms , IBM Microelectronics Division
Darren Anand , IBM Microelectronics Division
George Belansek , IBM Microelectronics Division
Jeffrey Leach , IBM Microelectronics Division
Gary Pomichter , IBM Microelectronics Division
Jeffrey Dreibelbis , IBM Microelectronics Division
Peter Jakobsen , IBM Microelectronics Division
John Barth , IBM Microelectronics Division
pp. 975

Shadow Write and Read For At-Speed BIST Of TDM SRAMs (Abstract)

Liviu Calin , Nortel Networks
Yuejian Wu , Nortel Networks
pp. 985

Memory Built-In Self-Repair using redundant words (Abstract)

Olivier Picot , Infineon Technologies AG
Steffen Paul , Infineon Technologies AG
Volker Schöber , Infineon Technologies AG
pp. 995
SESSION 36: LECTURE SERIES mdash; LOGIC BIST CASE STUDIES

null (PDF)

pp. null

An Effort-Minimized Logic BIST Implementation Method (Abstract)

Jan A. Tofte , Mentor Graphics Corp.
Xinli Gu , Cisco Systems, Inc.
Hamid Rahmanian , Mentor Graphics Corp.
Frank Tsang , Cisco Systems, Inc.
Sung Soo Chung , Cisco Systems, Inc.
pp. 1002

BIST and Fault Insertion Re-use in Telecom Systems (Abstract)

Snezana Dikic , Ericsson AsiaPacificLab
Lars-Johan Fritz , Ericsson Utvecklings AB
Dario Dell?Aquia , Ericsson Lab
pp. 1011

USE OF BIST IN SUN FIRE<sup>TM</sup> SERVERS (Abstract)

Brian Smith , Sun Microsystems, Inc.
Qing Lin , Sun Microsystems, Inc.
John Braden , Sun Microsystems, Inc.
pp. 1017
SESSION 37: ADVANCED METHODS IN EMBEDDED CORE TEST

null (PDF)

pp. null

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip (Abstract)

Erik Jan Marinissen , Philips Research Laboratories
Vikram Iyengar , Duke University
Krishnendu Chakrabarty , Duke University
pp. 1023

Configuration Free SoC Interconnect BIST Methodology (Abstract)

Chauchin Su , National Central University
Wenliang Tseng , National Central University
pp. 1033
SESSION 38: HOW COULD WE MODEL AND TEST VDSM DEFECTS

null (PDF)

pp. null

Boolean and Current Detection of MOS Transistor with Gate Oxide Short (Abstract)

Y. Bertrand , Universit? de Montpellier II
J.M. Gallière , Universit? de Montpellier II
F. Azaïs , Universit? de Montpellier II
M. Renovell , Universit? de Montpellier II
pp. 1039

Testing for Resistive Opens and Stuck Opens (Abstract)

Chao-Wen Tseng , Stanford University
James C.-M. Li , Stanford University
E.J. McCluskey , Stanford University
pp. 1049

An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test (Abstract)

Yasuo Sato , Hitachi, Ltd.
Iwao Yamazaki , Hitachi, Ltd.
Toshio Ikeda , Hitachi, Ltd.
Masaki Kohno , Hitachi, Ltd.
Masato Hamamoto , Hitachi, Ltd.
pp. 1059
SESSION 39: PRACTICAL TEST GENERATION TECHNIQUES

null (PDF)

pp. null

Fast Test Generation for Circuits with RTL and Gate-Level Views (Abstract)

Srivaths Ravi , Princeton University
Niraj K. Jha , Princeton University
pp. 1068

Combinational Test Generation for Various Classes of Acyclic Sequential Circuits (Abstract)

Vishwani D. Agrawal , CAS Res. Lab, Agere Systems
Kewal K. Saluja , University of Wisconsin-Madison
Yong Chang Kim , University of Wisconsin-Madison
pp. 1078

On Static Test Compaction and Test Pattern Ordering for Scan Designs (Abstract)

Xijiang Lin , Mentor Graphics Corp.
Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
Janusz Rajski , Mentor Graphics Corp.
pp. 1088
SESSION 40: DELVING INTO FACTORS AFFECTING MANUFACTURING COST

null (PDF)

pp. null

Tackling Test Trade-offs from Design, Manufacturing to Market using Economic Modeling (Abstract)

Erik H. Volkerink , Agilent Laboratories; MESA Research Institute
Ajay Khoche , Agilent Laboratories
Linda A. Kamas , Agilent Laboratories
Hans G. Kerkhoff , MESA Research Institute
Jochen Rivoir , Agilent Laboratories
pp. 1098

A New Test/Diagnosis/Rework Model for Use in Technical Cost Modeling of Electronic Systems Assembly (Abstract)

Peter Sandborn , University of Maryland
Ravi Raghavan , University of Maryland
Shubhada Sahasrabudhe , University of Maryland
Thiagarajan Trichy , University of Maryland
pp. 1108
SESSION 41: ATE HARDWARE: FROM GIGAHERTZ TO TERAHERTZ

null (PDF)

pp. null

Pin Electronics IC for High Speed Differential Devices (Abstract)

Atsushi Oshima , Schlumberger Semiconductor Solutions
Toshihiro Nomura , Schlumberger Semiconductor Solutions
John Poniatowski , Schlumberger Semiconductor Solutions
pp. 1128

Terabit-per-second Automated Digital Testing (Abstract)

D.C. Keezer , Georgia Institute of Technology
J. Kuan , Semiconductor Products Group
C. Bair , Semiconductor Products Group
Q. Zhou , Georgia Institute of Technology
B. Poole , Semiconductor Products Group
pp. 1143
PANEL 1: SEARCHING FOR COMMON GROUND BETWEEN LOW-COST AND HIGH-PERFORMANCE ATE SYSTEMS

Common Grounds for Varied Testers (PDF)

Gordon D Robinson , Third Millennium Test Solutions
pp. 1156

What are the right criteria for ATE? (PDF)

Anjali Kinra , Texas Instruments
pp. 1157
PANEL 2: OPEN MICROPHONE — WANTED: NEW TEST DIRECTIONS AND PRACTICAL TEST BOTTLENECKS
PANEL 3: CAN ANYONE STILL AFFORD SYSTEM TEST?
PANEL 4: THE CHALLENGES OF MANAGING TEST

THE CHALLENGES OF MANAGING TEST (PDF)

Atul Goel , Agilent Technologies, Inc.
pp. 1161

Challenges of Managing Test (PDF)

John L. Harris , IBM Microelectronics
pp. 1162

THE CHALLENGES OF MANAGING TEST: STANDARDIZATION (PDF)

Hwei-tsu Ann Luh , Taiwan Semiconductor Manufacturing Company
pp. 1163
PANEL 5: IS STRIP TESTING THE NEXT ADVANCE FOR SEMICONDUCTOR TEST?
PANEL 6: SYSTEM-IN-A-PACKAGE IS COMING TO CONSUMER PRODUCTS — IS TEST READY?

The SIP Alternative (PDF)

Larry Gilg , Die Products Consortium
pp. 1169
PANEL 7: AC SCAN: MICROPROCESSORS ARE READY...BUT WHERE IS THE INFRASTRUCTURE?
PANEL 8: DFT-CORRECT BY CONSTRUCTION OR MAKE IT WORK?

Can DFT be "Correct by Construction"? (PDF)

Robert C. Aitken , Agilent Technologies
pp. 1176
PANEL 9: LOWERING THE COST OF TEST: ATPG VS. BIST

The DFT Cost Dilemma (PDF)

Scott Davidson , Sun Microsystems Inc.
pp. 1182

Scan-Based ATPG or Logic BIST? (PDF)

T. W. Williams , Synopsys, Inc.
pp. 1183
PANEL 10: STANDARDIZED TESTING OF AC-COUPLED ICS ON HIGH-SPEED BOARDS AND SYSTEMS

Testing Differential Signals (PDF)

Carl F. Barnhart , IBM Corporation
pp. 1185
2000 ITC BEST PAPER:
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