The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (2000)
Atlantic City, NJ, USA
Oct. 3, 2000 to Oct. 5, 2000
ISSN: 1089-3539
ISBN: 0-7803-6546-1
TABLE OF CONTENTS
INTRODUCTORY SECTION

Author Index (PDF)

pp. 1157
SPECIAL PANEL: THE PRESS STRIKES BACK
SESSION 1: PLENARY

null (PDF)

pp. null
SESSION 2: SYSTEM TEST-LECTURE SERIES

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pp. null

On-Line and Off-Line Test of Airborne Digital Systems: a Reliability Study (Abstract)

Jacob Savir , New Jersey Institute of Technology University Heights
pp. 35

The Implementation of IEEE Std 1149.1 Boundary Scan Test Strategy within a Cellular Infrastructure Production Environment (Abstract)

Peter Collins , Motorola Network Solution Sector
Stephen Harrison , Motorola Network Solution Sector
Greg Noeninckx , Motorola Network Solution Sector
pp. 45
SESSION 3: ATE SOFTWARE GENERATION

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pp. null

Bridging the Gap Between Embedded Test and ATE (Abstract)

Stephen Pateras , LogicVision, Inc.
Givargis Danialy , LogicVision, Inc.
Michael Howells , LogicVision, Inc.
Martin Bell , LogicVision, Inc.
pp. 55
SESSION 4: DEFECT BEHAVIOR AND ANALYSIS TECHNIQUES

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pp. null

OPTICAL INTERFEROMETRIC PROBING OF ADVANCED MICROPROCESSORS (Abstract)

G. Xiao , Checkpoint Technologies
W.K. Lo , Schlumberger Technologies
T. M. Eiles , Intel Corporation
K. Wilsher , Schlumberger Technologies
pp. 80

Testing for Tunneling Opens (Abstract)

Edward J. McCluskey , Stanford University
James C.M. Li , Stanford University
pp. 85

DELAY-FAULT TESTING AND DEFECTS IN DEEP SUB-MICRON ICS - DOES CRITICAL RESISTANCE REALLY MEAN ANYTHING? (Abstract)

Will Moore , Dept. Engineering Science
Maurice Lousberg , Philips Research Laboratories
Keith Baker , Philips Research Laboratories
Guido Gronthoud , Philips Research Laboratories
pp. 95
SESSION 5: BIST: INDUSTRIAL APPLICATIONS

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pp. null

Application of Deterministic Logic BIST on Industrial Circuits (Abstract)

Gundolf Kiefer , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
Harald Vranken , Philips Research Laboratories
Erik Jan Marinisse , Philips Research Laboratories
pp. 105

REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS (Abstract)

Debaleena Das , University of Texas, Austin, TX 78712
Nur A. Touba , University of Texas, Austin, TX 78712 and Cores and System Technology
pp. 115

Test Structure Verification of Logical BIST: Problems and Solutions (Abstract)

Don Pearl , Test Design Automation, IBM Corp.
James Sage , Test Design Automation, IBM Corp.
Alan Troidl , Test Design Automation, IBM Corp.
Michael Cogswell , Test Design Automation, IBM Corp.
pp. 123
SESSION 6: MICROPROCESSOR TEST

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pp. null

DFT Advances in Motorola?s Next-Generation 74xx PowerPC™ Microprocessor (Abstract)

Javier Prado , Motorola Inc.; Somerset Design Center
Vikram Khosa , Motorola Inc.; Somerset Design Center
Ashutosh Razdan , Motorola Inc.; Somerset Design Center
Rajesh Raina , Motorola Inc.; Somerset Design Center
Robert Molyneaux , Motorola Inc.; Somerset Design Center
Robert Bailey , Motorola Inc.; Somerset Design Center
Dawit Belete , Motorola Inc.; Somerset Design Center
pp. 132

Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC™-III Microprocessor (Abstract)

Farideh Golshan , Processor Product Group, Sun Microsystems Inc., Palo Alto, CA
pp. 141
SESSION 7: SYSTEMS TEST

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pp. null

Si-Emulation: System Verification Using Simulation and Emulation (Abstract)

Zan Yang , Electrical Engineering Department, Texas A&M University
Gwan Choi , Electrical Engineering Department, Texas A&M University
Byeong Min , Electrical Engineering Department, Texas A&M University
pp. 160

Software Development Kit for Dependable Applications in Embedded (Abstract)

Politecnico di Torino , Dipartimento di Automatica e Informatica
pp. 170

COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS (Abstract)

Subhasish Mitra , Stanford University, Stanford, California
Edward J. McCluskey , Stanford University, Stanford, California
pp. 179
SESSION 8: PRACTICALI TESTING FOR DEEP-SUBMICRON DESIGNS

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pp. null

VARIANCE REDUCTION USING WAFER PATTERNS in I<sub>ddQ</sub> DATA (Abstract)

Kevin Cota , Electrical and Computer Engineering, Portland State University
Daniel Bockelman , Electrical and Computer Engineering, Portland State University
W. Robert Daasch , LSI Logic Corporation
James McNames , Electrical and Computer Engineering, Portland State University
pp. 189

DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ (Abstract)

Yukio Okuda , Semiconductor Company, Sony Corp.
pp. 199

Improving Delta-I<sub>DDQ</sub>-based test methods (Abstract)

C. Thibeault , ?cole de Technologie Sup?rieure
pp. 207

Increasing the IDDQ Test Resolution Using Current Prediction (Abstract)

Pramodchandran N. Variyam , Texas Instruments, MS 8727, 12500, TI Boulevard, Dallas, TX 75243
pp. 217
SESSION 9: FAULT DIAGNOSIS ALGORITHMS AND TECHNIQUES

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pp. null

Diagnostic Test Generation for Sequential Circuits (Abstract)

Jue Wuz , Sun Microsystems, Menlo Park, CA
Xiaoming Yuy , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Elizabeth M. Rudnicky , Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
pp. 225

An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction (Abstract)

Toshio Ishiyama , Analysis Technology Development Division, NEC
Kazuki Shigeta , Analysis Technology Development Division, NEC
pp. 235

Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application (Abstract)

Pankaj Pant , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 245

POIROT<sup>1</sup>: A Logic Fault Diagnosis Tool and Its Applications (Abstract)

Srikanth Venkataraman , Intel Corporation, Hillsboro, OR and Santa Clara, CA
Scott B. Drummonds , Intel Corporation, Hillsboro, OR and Santa Clara, CA
pp. 253
SESSION 10: BIST TECHNIQUES AND APPLICATIONS

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pp. null

Efficient Test Mode Selection & Insertion for RTL-BIST (Abstract)

Gokhan Guner , Department of ECE University of California
Kwang-Ting(Tim) Cheng , Department of ECE University of California
Subrata Roy , Department of ECE University of California
pp. 263

Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST (Abstract)

Ismet Bayraktaroglu , Computer Science & Engineering Department University of California, San Diego
Alex Orailoglu , Computer Science & Engineering Department University of California, San Diego
pp. 273

A BIST Approach for Very Deep Sub-Micron (VDSM) Defects (Abstract)

Yasuo Sato , Device Development Center, Hitachi, Ltd. , Ome-shi, Tokyo, Japan
Michinobu Nakao , Central Research Laboratory, Hitachi, Ltd. , Kokubunnji-shi, Tokyo, Japan
Takaharu Nagumo , Enterprise Server Division, Hitachi, Ltd. , Hadano-shi, Kanagawa, Japan
Toyohito Ikeya , Device Development Center, Hitachi, Ltd. , Ome-shi, Tokyo, Japan
pp. 283

Test Point Insertion for Compact Test Sets (Abstract)

J. Th. van de Linden , Scientificial, Delft, The Netherlands
A.J. van de Goor , Delft University of Technology, Faculty of Information Technology and Systems,
M.J. Geuzebroek , Delft University of Technology, Faculty of Information Technology and Systems,
pp. 292
SESSION 11: DESIGN VALIDATION: FROM FUNCTION TO TIMING

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pp. null

A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions (Abstract)

Qiushuang Zhang , University of Massachusetts
Ian G. Harris , University of Massachusetts
pp. 302

Static Property Checking Using ATPG v.s. BDD Techniques (Abstract)

Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Chung-Yang (Ric) Huang , University of California, Santa Barbara
Bwolen Yang , Verplex Systems, Inc.
Huan-Chih Tsai , Verplex Systems, Inc.
pp. 309

On Validating Data Hold Times for Flip-Flops in Sequential Circuits (Abstract)

Mitsuyasu Ohta , Corporate Semiconductor Development Division
Sudhakar M. Reddy , University of Iowa
Sadami Takeoka , Corporate Semiconductor Development Division
Atsushi Murakami , Kyushu Institute of Technology
Seiji Kajihara , Kyushu Institute of Technology
Irith Pomeranz , University of Iowa
pp. 317

Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays (Abstract)

Sandeep K. Gupta , University of Southern California
Nabil M. Abdulrazzaq , University of Southern California
pp. 326
SESSION 12: DEFECT-BASED TEST METHODOLOGIES AND THE REAL WORLD-LECTURE SERIES

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pp. null

Stuck-Fault Tests vs. Actual Defects (Abstract)

Chao-Wen Tseng , Stanford University, Stanford, CA 94305
Edward J. McCluskey , Stanford University, Stanford, CA 94305
pp. 336
SESSION 13: TEST TECHNIQUES FOR ADCS

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pp. null

Measuring Code Edges of ADCs Using Interpolation and Its Application to Offset and Gain Error Testing (Abstract)

Vinay Agrawal , Texas Instruments Inc., Dallas, TX.
Pramodchandran N. Variyam , Texas Instruments Inc., Dallas, TX.
pp. 349

OPTIMAL ANALOG TRIM TECHNIQUES FOR IMPROVING THE LINEARITY OF PIPELINE ADCs (Abstract)

Frank Tsay , Texas Instruments Inc.
Turker Kuyel , Texas Instruments Inc.
pp. 367
SESSION 14: DELAY FAULT TESTING

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pp. null

Selection of Potentially Testable Path Delay Faults for Test Generation (Abstract)

Seiji Kajihara , Kyushu Institute of Technology
Tsutomu Sasao , Kyushu Institute of Technology
Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
Atsushi Murakami1 , Kyushu Institute of Technology
pp. 376

ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS (Abstract)

Janak H. Patel , University of Illinois at Urbana-Champaign
Manish Sharma , University of Illinois at Urbana-Champaign
pp. 385
SESSION 15: OPTIMIZING TEST EFFECTIVENESS

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pp. null

Comparing Functional and Structural Tests (Abstract)

Ismed Hartanto , Agilent Technologies
Peter Maxwell , Agilent Technologies
Lee Bentz , Agilent Technologies
pp. 400

An Empirical Study on the Effects of Test Type Ordering on (Abstract)

Jayashree Saxena , Texas Instruments Inc.
Kenneth M. Butler , Texas Instruments Inc.
pp. 408

A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx (Abstract)

Srinivasa Chakravarthy B.S , Texas Instruments
Narayan Prasad , Texas Instruments
Rubin A. Parekhji , Texas Instruments
Ameet Bagwe , Texas Instruments
Jais Abraham , Texas Instruments
pp. 417
SESSION 16: MEMORY TESTING

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pp. null

Industrial Evaluation of DRAM SIMM Tests (Abstract)

Ad J. van de Goor , Delft University of Technology, Faculty of Information Technology and Systems
Alexander Paalvast , Delft University of Technology, Faculty of Information Technology and Systems
pp. 426

DESIGN-FOR-TEST METHODS FOR STAND-ALONE SRAMS AT 1Gb/s/pin AND BEYOND (Abstract)

Harold Pilo , IBM Microelectronics Division
Chris Murphy , IBM Microelectronics Division
Steve Lamphier , IBM Microelectronics Division
Patrick Hansen , IBM Microelectronics Division
Stu Hall , IBM Microelectronics Division
pp. 436
SESSION 17: DEFECT-BASED TEST METHODOLOGIES AND THE REAL WORLD-LECTURE SERIES

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pp. null

Test Method Evaluation Experiments & Data (Abstract)

Anne Gattiker , IBM Austin Research Lab
Phil Nigh , IBM Microelectronics
pp. 454
SESSION 18: FROM TESTER TO APPLICATIONS-BEGINNING TO END

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pp. null

A NEW PARADIGM IN TEST FOR THE NEXT MILLENNIUM (Abstract)

Jerry Katz , Advantest America R & D Center, Inc.
Rochit Rajsuman , Advantest America R & D Center, Inc.
pp. 468

REDUCING DEVICE YIELD FALLOUT AT WAFER LEVEL TEST WITH ELECTROHYDRODYNAMIC (EHD) CLEANING (Abstract)

Reynaldo M. Rincon , Texas Instruments Corporation, Dallas, TX 75243
James C. Andersen, Ph.D , Applied Precision Incorporated, Issaquah, WA 98027
Jerry J. Broz , Texas Instruments Corporation, Dallas, TX 75243
pp. 477
SESSION 19: TESTS FOR CROSSTALK AND BRIDGING FAULTS

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pp. null

Analysis of Interconnect Crosstalk Defect Coverage of Test Sets (Abstract)

Sujit Dey , University of California, San Diego, La Jolla, CA 92093-0407
Yi Z hao , University of California, San Diego, La Jolla, CA 92093-0407
pp. 492

Identification of Crosstalk Switch Failures in Domino CMOS Circuits (Abstract)

Rahul Kundu , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 502
SESSION 20: ADVANCES IN TEST GENERATION

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pp. null

Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis (Abstract)

Hideo Fujiwara , Grad. Seh. of Inform. Sci.
Yi Xu , Tsinghua University
Dong Xiang , Tsinghua University
pp. 520

Design and Implementation of a Parallel Automatic Test Pattern Generation Algorithm with Low Test Vector Count (Abstract)

Richard Schoonover , IBM MicroElectronics Division
Brion Keller , IBM MicroElectronics Division
Sarala Paliwal , IBM MicroElectronics Division
Robert Butler , IBM MicroElectronics Division
pp. 530

EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS (Abstract)

Mark W. Weiss , University of Nebraska-Lincoln
Shashank K. Mehta , Pune University
Kent L. Einspahr , Concordia University
Sharad C. Seth , University of Nebraska-Lincoln
pp. 538
SESSION 21: EMBEDDED MEMORIES TEST AND REPAIR

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pp. null

Self Test Architecture for Testing Complex Memory Structures (Abstract)

Kamran Zarrineh , Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
Steven P. Gregor , Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
R. Dean Adams , Design-For-Test Group, IBM Microelectronics, Essex Junction, VT
Thomas J. Eckenrode , Test Design Automation (TDA), IBM Microelectronics, Endicott, NY
pp. 547

A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs (Abstract)

Tukas Ooishi , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Jun Ohtani , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Mitsuhiro Hamada , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Hideto Hidaka , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Mitsutaka Niiro , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
Tomoya Kawagoe , Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.,
pp. 567
SESSION 22: BOARD TEST

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pp. null

Power Pin Testing: Making the Test Coverage Complete (Abstract)

Ben Kup , Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
Frans de Jong , Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
Rodger Schuttert , Integrated Circuit Laboratory, Philips Consumer Electronics, The Netherlands
pp. 575

End-to-End Testing for Boards and Systems Using Boundary Scan (Abstract)

Robert W. Barr , Lucent Technologies
Edward L. Wallace , Lucent Technologies
Chen-Huan Chiang , Lucent Technologies
pp. 585

MOTHERBOARD TESTING USING THE PCI-BUS (Abstract)

David McClintock , The University of Texas at Austin
Lance Cunningham , The University of Texas at Austin
Takis Petropoulos , The University of Texas at Austin
pp. 593
SESSION 23: TESTER HARDWARE ISSUES IN LEAPING TO 1GHZ

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pp. null

DIGITAL SERIAL COMMUNICATION DEVICE TESTING AND ITS IMPLICATIONS ON AUTOMATIC TEST EQUIPMENT ARCHITECTURE (Abstract)

E. Masserrat , Lucent Technologies - Bell Laboratories
T. P. Warwick , Evaluation and Product Engineering, Inc.
S. G. Rane , Lucent Technologies - Bell Laboratories
Y. Cai , Lucent Technologies - Bell Laboratories
pp. 600
SESSION 24: SOC TEST SOLUTIONS

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pp. null

Using On-chip Test Pattern Compression For Full Scan SoC Designs (Abstract)

Jens Pfeiffer , Motorola, Inc.
Helmut Lang , Motorola, Inc.
Jeff Maguire , Motorola, Inc.
pp. 638

Non-Intrusive BIST for Systems-on-a-Chip (Abstract)

Silvia CHIUSANO , Politecnico di Torino
PAOLO PRINETTO , Politecnico di Torino
HANS-JOACHIM WUNDERLICH , University of Stuttgart
pp. 644
SESSION 25: LOW-POWER BIST

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pp. null

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures (Abstract)

P. Girard , Universit? Montpellier II / CNRS
C. Landrault , Universit? Montpellier II / CNRS
S. Pravossoudovitch , Universit? Montpellier II / CNRS
L. Guiller , Universit? Montpellier II / CNRS
pp. 652

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths (Abstract)

Bashir M. Al-Hashimi , Electronic Systems Design Group
Nicola Nicolici , Electronic Systems Design Group
pp. 662
SESSION 26: METHODOLOGY AND TOOLS FOR MICROPROCESSOR TEST

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pp. null

Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns (Abstract)

Tim Wood , Advanced Micro Devices
Don E. Ross , Mentor Graphics Corporation
Grady Giles , Advanced Micro Devices
pp. 691

Logic Mapping on a Microprocessor (Abstract)

John Carulli , Texas Instruments Inc.
Hari Balachandran , Texas Instruments Inc.
Regy Thomas , Texas Instruments Inc.
Anjali Kinra , Texas Instruments Inc.
pp. 701
SESSION 27: BOARD TEST-LECTURE SERIES

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pp. null

IT ISN'T JUST TESTING ANYMORE (REDUX) (Abstract)

Stephen F. Scheiber , ConsuLogic Consulting Services, 276 Longhouse Lane, Slingerlands, NY 12159-3012
pp. 718

System Issues in Boundary-Scan Board Test (Abstract)

Kenneth P. Parker , Agilent Technologies
pp. 724
SESSION 28: EXTRACTION TEST AND DIAGNOSIS OF PHYSICAL DEFECTS

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pp. null

Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis (Abstract)

Sri Jandhyala , Texas Instruments, Inc.
Zoran Stanojevic , Texas A&M University
Kenneth M. Butler , Texas Instruments, Inc.
Fred Lakhani , International Sematech
D. M. H. Walker , Texas A&M University
Jayashree Saxena , Texas Instruments, Inc.
Hari Balachandran , Texas Instruments, Inc.
pp. 729

Analysis of Failure Sources in Surface-Micromachined MEMS (Abstract)

N. Deb , Carnegie Mellon University
R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 739

Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development (Abstract)

James R. Bailey , University of Kentucky
John M. Emmert , University of North Carolina at Charlotte
Charles E. Stroud , University of North Carolina at Charlotte
Khushru S. Chhor , Cypress Semiconductor
Dragomir Nikolic , Cypress Semiconductor
pp. 760
SESSION 29: USE MODELS OF IEEE P1500

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pp. null

On Using IEEE P1500 SECT for Test Plug-n-Play (Abstract)

Rohit Kapur , Synopsys, Inc.
Yervant Zorian , LogicVision, Inc.
Erik Jan Marinissen , Philips Research Laboratories
pp. 770
SESSION 30: QUALITY BIST FOR LOGIC AND FPGA

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pp. null

A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS (Abstract)

Hua-Guo Liang , University of Stuttgart
Sybille Hellebrand , University of Innsbruck
Hans-Joachim Wunderlich , University of Stuttgart
pp. 778

BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs (Abstract)

Charles Stroud , Dept. of Electrical Engineering - University of Kentucky
Miron Abramovici , Bell Labs - Lucent Technologies
pp. 785

NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS (Abstract)

Ben Chan , University of Alberta
Xiaoling Sun , University of Alberta
Jian Xu , University of Alberta
Pieter Trouborst , Microelectronics Group, Nortel Networks
pp. 795

Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register (Abstract)

D. Nikolos , Dept. of Computer Engineering and Informatics, University of Patras, Computer Technology Institute, 3, Kolokotroni Str., 262 61 Patras, Greece
X. Kavousianos , Dept. of Computer Engineering and Informatics, University of Patras, 26 500, Rio, Greece
D. Bakalis , Dept. of Computer Engineering and Informatics, University of Patras, Computer Technology Institute, 3, Kolokotroni Str., 262 61 Patras, Greece
pp. 804
SESSION 31: DETECTING ALL TYPES OF FAULTS QUICKLY

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pp. null

Universal Test Generation Using Fault Tuples (Abstract)

Rao Desineni , Carnegie Mellon University, Pittsburgh, PA 15213
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA 15213
Kumar N. a Dwarkanath , Carnegie Mellon University, Pittsburgh, PA 15213
pp. 812

Reducing Test Application Time in High-Level Test Generation (Abstract)

Niraj K. Jha , Princeton University, Princeton, NJ 08544
Srivaths Ravi , Princeton University, Princeton, NJ 08544
Ganesh Lakshminarayana , NEC USA, Inc., Princeton, NJ 08536
pp. 829
SESSION 32: FPGA TESTING-LECTURE SERIES

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pp. null
SESSION 33: TEST TECHNIQUES FOR LOW-POWER OPTIMIZATION

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pp. null

Optimization Trade-offs for Vector Volume and Test Power (Abstract)

Bahram Pouya , Motorola, ColdFire Core Technology Center
Alfred L. Crouch , Motorola, ColdFire Core Technology Center
pp. 873

A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling (Abstract)

Valentina Muresan , "Politehnica" University of Timisoara, Romania
Xiaojun Wang , Dublin City University, Ireland
Mircea Vladutiu , "Politehnica" University of Timisoara, Romania
Valentin Muresan , Dublin City University, Ireland
pp. 882
SESSION 34: TEST ACCESS DESIGN FOR SOC'S

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pp. null

HD2BIST: a Hierarchical Framework for BIST Scheduling, Data patterns delivering and diagnosis in SoCs (Abstract)

Stefano DI CARLO , Politecnico di Torino
Silvia CHIUSANO , Politecnico di Torino
Alfredo BENSO , Politecnico di Torino
Paolo PRINETTO , Politecnico di Torino
Fabio RICCIATO , Politecnico di Torino
pp. 892

An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing (Abstract)

Christos Papachristou , Case Western Reserve Univ.
Mehrdad Nourani , The Univ. of Texas at Dallas
pp. 902

Wrapper Design for Embedded Core Test (Abstract)

Maurice Lousberg , Philips Research Laboratories
Erik Jan Marinissen , Philips Research Laboratories
Sandeep Kumar Goel , Indian Institute of Technology
pp. 911
SESSION 35: HOW DO WE KNOW IF FAULT MODELS ARE ACCURATE?

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pp. null

Deception by Design: Fooling Ourselves with Gate-level Models (Abstract)

Jeff Rearick , Agilent Technologies
Peter Maxwell , Agilent Technologies
pp. 921

Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D (Abstract)

Micheal R. Grimaila , Texas A&M University, College Station, Texas
M. Ray Mecer , Texas A&M University, College Station, Texas
Jennifer Dworak , Texas A&M University, College Station, Texas
Li-C. Wang , Texas A&M University, College Station, Texas
Sooryong Lee , Texas A&M University, College Station, Texas
pp. 930

REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS (Abstract)

Pradip A. Thaker , Hughes Network Systems
Mona E. Zaghloul , George Washington University
Vishwani D. Agrawal , Bell Labs, Lucent Technologies
pp. 940
SESSION 36: HIGH-FREQUENCY TEST TECHNIQUES

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pp. null

Microwave Test Mismatch and Power De-embedding (Abstract)

Peter Higgins , Intersil/Teradyne
Jim Lampos , Intersil
pp. 950

Jitter Measurements of a PowerPC™ Microprocessor Using an Analytic Signal Method (Abstract)

Mani Soma , Department of Electrical Engineering, University of Washington, Seattle, WA
David Halter , Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Jim Nissen , Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Masahiro Ishida , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Rajesh Raina , Somerset PowerPC Design Center, Motorola Inc., Austin, TX
Toshifumi Watanabe , Advantest Corporation, Ora, Gunma, Japan
pp. 955

Technique For Testing A Very High Speed Mixed Signal Read Channel Design (Abstract)

Doug Matthes , Texas Instruments, Inc.
John Ford , Texas Instruments, Inc.
pp. 965
SESSION 37: CONCURRENT ERROR DETECTION

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pp. null

Concurrent Error Detection in Block Ciphers (Abstract)

J.J. Rodr?guez-Andina , University of Vigo
E. Mandado , University of Vigo
Santiago Fern?ndez-G?mez , ATI Research Silicon Valley, Inc.
pp. 979

WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE? (Abstract)

Subhasish Mitra , Stanford University, Stanford, California
Edward J. McCluskey , Stanford University, Stanford, California
pp. 985
SESSION 38: THE FINAL HURDLE-SIGNALS AND POWER TO THE DUT

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pp. null

Structural Test in a Board Self Test Environment (Abstract)

Ulf Pillkahn , Siemens AG Munich, Germany
pp. 1005

Challenges of High Supply Currents During VLSI Test (Abstract)

Gerald H. Johnson , Teradyne Inc., 5301 East River Road, Fridley, MN 55421
pp. 1013
SESSION 39: MIXED-SIGNAL BIST

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pp. null

Testing and Characterization of the One-Bit First-Order Delta-Sigma (Abstract)

Jiun-Lang Huang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 1021

Digital Signature Proposal for Mixed-Signal Circuits (Abstract)

Joan Figueras , Electronics Dept. Universitat Polit?cnica de Catalunya
Anna Maria Brosa , Electronics Dept. Universitat Polit?cnica de Catalunya
pp. 1041
SESSION 40: NEW METHODS FOR DELAY TESTING

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pp. null

Multiple-Parameter CMOS IC Testing with Increased Sensitivity for I<sub>DDQ</sub> (Abstract)

Manoj Sachdev , University of Waterloo,
K. Soumyanath , Microprocessor Research Labs, Intel Corporation
Vivek De , Microprocessor Research Labs, Intel Corporation
Charles F. Hawkins , The University of New Mexico
Ali Keshavarzi , Microprocessor Research Labs, Intel Corporation
Kaushik Roy , Purdue University,
pp. 1051

An Analysis of the Delay Defect Detection Capability of the ECR Test Method (Abstract)

Sreejit Chakravarty , Intel Corporation
Bapiraju Vinnakota , University of Minnesota, Minneapolis, Minnesota
Seonki Kim , University of Minnesota, Minneapolis, Minnesota
pp. 1060

Predicting Device Performance From Pass/Fail Transient Signal Analysis Data (Abstract)

Amy Germida , Department of CSEE, University of Maryland, Baltimore County
Chintan Patel , Department of CSEE, University of Maryland, Baltimore County
Jonathan Hudson , Department of CSEE, University of Maryland, Baltimore County
Ernesto Staroswiecki , Department of CSEE, University of Maryland, Baltimore County
Jim Plusquellic , Department of CSEE, University of Maryland, Baltimore County
pp. 1070
SESSION 41: PROCESSOR CORE TEST TECHNIQUES

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pp. null

Test Program Synthesis for Path Delay Faults in Microprocessor Cores (Abstract)

Angela Krstic , Department of ECE, University of California, Santa Barbara, CA 93106
Kwang-Ting (Tim) Cheng , Department of ECE, University of California, Santa Barbara, CA 93106
Wei-Cheng Lai , Department of ECE, University of California, Santa Barbara, CA 93106
pp. 1080
PANEL 1: FUTURE CHALLENGES FOR SYSTEM TEST
PANEL 2: INTERNAL CAD + EDA + SERVICES = TURMOIL, FENCING OR BLISS

Click Here for Silicon !! (PDF)

Ismed Hartanto , Agilent Technologies, Santa Clara, CA
pp. 1110

EDA vs. NIH: Where?s the Value? (PDF)

Cy Hay , Synopsys, Inc.
pp. 1111
PANEL 3: NOISE: WHOSE PROBLEM IS IT ANYWAY?

Noise: Whose Problem is it Anyway? (PDF)

Sandeep Gupta , Department of EE-Systems, USC, Los Angeles, CA
pp. 1113

Position Statement: Noise: Whose Problem Is It Anyway (PDF)

Melvin A. Breuer , University of Southern California
pp. 1114

It?s their problem - Not mine! (PDF)

Bill Grundmann , Compaq Computer Corporation
pp. 1115

Noise: Whose Problem Is It Anyway ? (PDF)

Sandip Kundu , Intel Corporation, MS AN1-2B17
pp. 1116

Noise: Whose problem is it anyway? (PDF)

Nagaraj NS , Texas Instruments Inc.,
pp. 1117
PANEL 4: DFT-FOCUSED CHIP TESTERS: WHAT CAN THEY REALLY DO?

DFT-Focused Chip Testers: What Can They Really Do? (PDF)

Gordon D Robinson , Credence Systems Corporation, Fremont CA
pp. 1119

DFT-Focused Chip Testers - What Can They Do? (PDF)

Steve Comen , Texas Instruments, Inc
pp. 1120

Enough Test with DFT-Focused Chip Testers (PDF)

Peter Muhmenthaler , Infineon Technologies AG
pp. 1122
PANEL 5: WHAT DEFECTS ESCAPE OUR TESTS . . . AND HOW WILL WE DETECT THEM IN THE FUTURE?

Getting Better Coverage from the Tests We Have (PDF)

Anjali Kinra , Texas Instruments Inc., 12203 Southwest Fwy, MS 706, Bldg2, Stafford TX 77477
pp. 1124
PANEL 6: GOOD DIE IN BAD NEIGHBORHOODS

Good Die in Bad Neighborhoods (PDF)

Jeffrey L. Roehr , Analog Devices, Wilmington Mass.
pp. 1126

Position Statement: Good Die in Bad Neighborhoods? (PDF)

Stefan Eichenberger , Philips Semiconductors, CH-8045 Zurich, Switzerland
pp. 1127

Position Statement: Good Die in Bad Neighborhoods (PDF)

Russell B. Miller , Intel Corporation, Chandler, AZ
pp. 1128

Position Statement: Good Die in Bad Neighborhoods (PDF)

Adit D. Singh , Department of Electrical & Computer Engineering
pp. 1129
PANEL 7: TESTING CHALLENGES FOR MEMS

Testing Challenges for MEMS (PDF)

Karen Panetta , Tufts University
pp. 1130

Challenges Facing MEMS Analysis (PDF)

N. R. Aluru , University of Illinois at Urbana-Champaign, Urbana, IL 61801
pp. 1131

TESTING AND METROLOGY IN THE ADOPTION OF MST/MEMS AS A MAINSTREAM TECHNOLOGY (PDF)

Stephen F. Bart , Microcosm Technologies, Inc., 215 First St. Cambridge, MA 02142, sbart@memcad.com
pp. 1132

The Challenge of MEMS Test (PDF)

R. D. (Shawn) Blanton , Carnegie Mellon University
pp. 1133

Biocompatibility and Lifespan of MEMS Bio-Implants (PDF)

Karl F. B?hringer , University of Washington, Seattle, WA
pp. 1134

SOLID-STATE LIQUID CHEMICAL SENSOR TESTING ISSUES (PDF)

Richard B. Brown , 2403 EECS, University of Michigan, Ann Arbor, MI 48109-2122
pp. 1135
PANEL 8: WIRELESS COMMUNICATION PRODUCTS MEANS A SYSTEM-ON-CHIP WITH RF HEADACHES FOR TESTING. WHERE IS THE MIRACLE PILL?
PANEL 9: BIG-IRON TESTERS ARE A REALITY-THEIR REQUIREMENTS AND ROLE

The Future of High-End ATE (PDF)

Ulrich Schoettmer , Agilent Technologies
pp. 1141
PANEL 10: CAN DFT TOTALLY ELIMINATE THE TRADITIONAL FUNCTIONAL TESTING?

PANEL: CAN D.F.T. Totally "Delete Functional Testing?" NOT LIKELY ! (PDF)

Burnell G. West , Schlumberger Semiconductor Solutions San Jose, California, USA
pp. 1146
1999 ITC BEST PAPER:

Current Ratios: A Self-Scaling Technique for Production IDDQ Testing (Abstract)

Pete O?Neill , Hewlett-Packard Company
Roland Dudley , Hewlett-Packard Company
Rob Aitken , Hewlett-Packard Company
Neal Jaarsma , Hewlett-Packard Company
Peter Maxwell , Hewlett-Packard Company
Minh Quac , Hewlett-Packard Company
pp. 1148
89 ms
(Ver )