Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) (2000)
Atlantic City, NJ, USA
Oct. 3, 2000 to Oct. 5, 2000
Steven F. Oakland , IBM Microelectronics Division
This paper addresses four issues associated with using IEEE Standard 1149.1 on system-on-a-chip integrated circuits (SOC ICs). First, a new, simplified method for accessing debug registers in processor cores embedded within ICs is presented. Second, structural information required by hardware/software processor development tools is presented. Third, issues associated with boundary-scan description language (BSDL) are discussed. Finally, highspeed boundary-scan cells that avoid a multiplexer delay are presented.
S. F. Oakland, "Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits," Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)(ITC), Atlantic City, NJ, USA, 2000, pp. 628.